reg2.vhd

来自「实现DDS频率可调得VHDL程序」· VHDL 代码 · 共 17 行

--REG2.VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG2 IS
	PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		CLK:IN STD_LOGIC;
		Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY REG2;
ARCHITECTURE TWO OF REG2 IS
BEGIN
	PROCESS(CLK)IS
	BEGIN
	IF(CLK'EVENT AND CLK='1')THEN
		Q<=D;
	END IF;
	END PROCESS;
END ARCHITECTURE TWO;