dds.fit.smsg

实现DDS频率可调得VHDL程序

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
    Info: Processing started: Mon May 26 17:55:42 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS
Info: Selected device EP1C3T144C8 for design "DDS"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 2 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 466 of 466 atoms in partition Top
    Info: Previous placement does not exist for 107 of 107 atoms in partition sld_hub:sld_hub_inst
Info: Detected 1 design partitions (excluding Top) used without floorplan location assignments.
    Info: Design partition sld_hub:sld_hub_inst has no floorplan location assignments
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Warning: No exact pin location assignment(s) for 19 pins of 19 total pins
    Info: Pin Q[0] not assigned to an exact location on the device
    Info: Pin Q[1] not assigned to an exact location on the device
    Info: Pin Q[2] not assigned to an exact location on the device
    Info: Pin Q[3] not assigned to an exact location on the device
    Info: Pin Q[4] not assigned to an exact location on the device
    Info: Pin Q[5] not assigned to an exact location on the device
    Info: Pin Q[6] not assigned to an exact location on the device
    Info: Pin Q[7] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin M[6] not assigned to an exact location on the device
    Info: Pin RESET not assigned to an exact location on the device
    Info: Pin EN not assigned to an exact location on the device
    Info: Pin M[7] not assigned to an exact location on the device
    Info: Pin M[5] not assigned to an exact location on the device
    Info: Pin M[4] not assigned to an exact location on the device
    Info: Pin M[0] not assigned to an exact location on the device
    Info: Pin M[1] not assigned to an exact location on the device
    Info: Pin M[2] not assigned to an exact location on the device
    Info: Pin M[3] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "CLK" to use Global clock in PIN 17
Info: Automatically promoted signal "altera_internal_jtag~TCKUTAP" to use Global clock
Info: Automatically promoted signal "RESET" to use Global clock in PIN 16
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|CLR_SIGNAL" to use Global clock
    Info: Destination "sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]" to use Global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~195" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" to use Global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]" may be non-global or may not use global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" may be non-global or may not use global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell" may be non-global or may not use global clock
Info: Automatically promoted signal "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0" to use Global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]" to use Global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~22" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~3903" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg~3907" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~10" may be non-global or may not use global clock
    Info: Destination "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]~3945" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 17 (unused VREF, 3.30 VCCIO, 9 input, 8 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  26 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Error: Selected device has 13 RAM location(s) of type M4K.  However, the current design needs more than 13 to successfully fit
    Info: List of RAM cells constrained to M4K locations
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a112"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a113"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a114"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a115"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a116"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a117"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a118"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a119"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a104"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a105"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a106"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a107"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a108"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a109"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a110"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a111"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a96"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a97"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a98"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a99"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a100"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a101"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a102"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a103"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a120"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a121"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a122"
        Info: Node "ROM:U2|altsyncram:altsyncram_component|altsyncram_qj51:auto_generated|altsyncram_2772:altsyncram1|ram_block3a123"