dds.fit.eqn

实现DDS频率可调得VHDL程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E1_q_a[0] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[0] at M4K_X13_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(CLK);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];

--E1_q_a[6] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[6] at M4K_X13_Y1
E1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(CLK);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[0]_PORT_A_data_out[3];

--E1_q_a[3] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[3] at M4K_X13_Y1
E1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(CLK);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[0]_PORT_A_data_out[2];

--E1_q_a[2] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[2] at M4K_X13_Y1
E1_q_a[0]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(CLK);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[0]_PORT_A_data_out[1];


--E1_q_a[1] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[1] at M4K_X13_Y2
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(CLK);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];

--E1_q_a[7] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[7] at M4K_X13_Y2
E1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(CLK);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[1]_PORT_A_data_out[3];

--E1_q_a[5] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[5] at M4K_X13_Y2
E1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(CLK);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[1]_PORT_A_data_out[2];

--E1_q_a[4] is rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4] at M4K_X13_Y2
E1_q_a[1]_PORT_A_address = BUS(~GND, ~GND, B1_TEMP[8], B1_TEMP[9], B1_TEMP[10], B1_TEMP[11], B1_TEMP[12], B1_TEMP[13], B1_TEMP[14], B1_TEMP[15]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(CLK);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[1]_PORT_A_data_out[1];


--B1_TEMP[8] is SUM:U0|TEMP[8] at LC_X15_Y1_N0
--operation mode is arithmetic

B1_TEMP[8]_lut_out = M[0] $ B1_TEMP[8];
B1_TEMP[8] = DFFEAS(B1_TEMP[8]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L3 is SUM:U0|TEMP[8]~73 at LC_X15_Y1_N0
--operation mode is arithmetic

B1L3_cout_0 = M[0] & B1_TEMP[8];
B1L3 = CARRY(B1L3_cout_0);

--B1L4 is SUM:U0|TEMP[8]~73COUT1_105 at LC_X15_Y1_N0
--operation mode is arithmetic

B1L4_cout_1 = M[0] & B1_TEMP[8];
B1L4 = CARRY(B1L4_cout_1);


--B1_TEMP[9] is SUM:U0|TEMP[9] at LC_X15_Y1_N1
--operation mode is arithmetic

B1_TEMP[9]_lut_out = B1_TEMP[9] $ M[1] $ B1L3;
B1_TEMP[9] = DFFEAS(B1_TEMP[9]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L6 is SUM:U0|TEMP[9]~77 at LC_X15_Y1_N1
--operation mode is arithmetic

B1L6_cout_0 = B1_TEMP[9] & !M[1] & !B1L3 # !B1_TEMP[9] & (!B1L3 # !M[1]);
B1L6 = CARRY(B1L6_cout_0);

--B1L7 is SUM:U0|TEMP[9]~77COUT1_106 at LC_X15_Y1_N1
--operation mode is arithmetic

B1L7_cout_1 = B1_TEMP[9] & !M[1] & !B1L4 # !B1_TEMP[9] & (!B1L4 # !M[1]);
B1L7 = CARRY(B1L7_cout_1);


--B1_TEMP[10] is SUM:U0|TEMP[10] at LC_X15_Y1_N2
--operation mode is arithmetic

B1_TEMP[10]_lut_out = B1_TEMP[10] $ M[2] $ !B1L6;
B1_TEMP[10] = DFFEAS(B1_TEMP[10]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L9 is SUM:U0|TEMP[10]~81 at LC_X15_Y1_N2
--operation mode is arithmetic

B1L9_cout_0 = B1_TEMP[10] & (M[2] # !B1L6) # !B1_TEMP[10] & M[2] & !B1L6;
B1L9 = CARRY(B1L9_cout_0);

--B1L01 is SUM:U0|TEMP[10]~81COUT1_107 at LC_X15_Y1_N2
--operation mode is arithmetic

B1L01_cout_1 = B1_TEMP[10] & (M[2] # !B1L7) # !B1_TEMP[10] & M[2] & !B1L7;
B1L01 = CARRY(B1L01_cout_1);


--B1_TEMP[11] is SUM:U0|TEMP[11] at LC_X15_Y1_N3
--operation mode is arithmetic

B1_TEMP[11]_lut_out = M[3] $ B1_TEMP[11] $ B1L9;
B1_TEMP[11] = DFFEAS(B1_TEMP[11]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L21 is SUM:U0|TEMP[11]~85 at LC_X15_Y1_N3
--operation mode is arithmetic

B1L21_cout_0 = M[3] & !B1_TEMP[11] & !B1L9 # !M[3] & (!B1L9 # !B1_TEMP[11]);
B1L21 = CARRY(B1L21_cout_0);

--B1L31 is SUM:U0|TEMP[11]~85COUT1 at LC_X15_Y1_N3
--operation mode is arithmetic

B1L31_cout_1 = M[3] & !B1_TEMP[11] & !B1L01 # !M[3] & (!B1L01 # !B1_TEMP[11]);
B1L31 = CARRY(B1L31_cout_1);


--B1_TEMP[12] is SUM:U0|TEMP[12] at LC_X15_Y1_N4
--operation mode is arithmetic

B1_TEMP[12]_lut_out = M[4] $ B1_TEMP[12] $ !B1L21;
B1_TEMP[12] = DFFEAS(B1_TEMP[12]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L51 is SUM:U0|TEMP[12]~89 at LC_X15_Y1_N4
--operation mode is arithmetic

B1L51 = B1L61;


--B1_TEMP[13] is SUM:U0|TEMP[13] at LC_X15_Y1_N5
--operation mode is arithmetic

B1_TEMP[13]_carry_eqn = (!B1L51 & GND) # (B1L51 & VCC);
B1_TEMP[13]_lut_out = M[5] $ B1_TEMP[13] $ B1_TEMP[13]_carry_eqn;
B1_TEMP[13] = DFFEAS(B1_TEMP[13]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L91 is SUM:U0|TEMP[13]~93 at LC_X15_Y1_N5
--operation mode is arithmetic

B1L91_cout_0 = M[5] & !B1_TEMP[13] & !B1L51 # !M[5] & (!B1L51 # !B1_TEMP[13]);
B1L91 = CARRY(B1L91_cout_0);

--B1L02 is SUM:U0|TEMP[13]~93COUT1_108 at LC_X15_Y1_N5
--operation mode is arithmetic

B1L02_cout_1 = M[5] & !B1_TEMP[13] & !B1L51 # !M[5] & (!B1L51 # !B1_TEMP[13]);
B1L02 = CARRY(B1L02_cout_1);


--B1_TEMP[14] is SUM:U0|TEMP[14] at LC_X15_Y1_N6
--operation mode is arithmetic

B1_TEMP[14]_carry_eqn = (!B1L51 & B1L91) # (B1L51 & B1L02);
B1_TEMP[14]_lut_out = B1_TEMP[14] $ M[6] $ !B1_TEMP[14]_carry_eqn;
B1_TEMP[14] = DFFEAS(B1_TEMP[14]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );

--B1L22 is SUM:U0|TEMP[14]~97 at LC_X15_Y1_N6
--operation mode is arithmetic

B1L22_cout_0 = B1_TEMP[14] & (M[6] # !B1L91) # !B1_TEMP[14] & M[6] & !B1L91;
B1L22 = CARRY(B1L22_cout_0);

--B1L32 is SUM:U0|TEMP[14]~97COUT1_109 at LC_X15_Y1_N6
--operation mode is arithmetic

B1L32_cout_1 = B1_TEMP[14] & (M[6] # !B1L02) # !B1_TEMP[14] & M[6] & !B1L02;
B1L32 = CARRY(B1L32_cout_1);


--B1_TEMP[15] is SUM:U0|TEMP[15] at LC_X15_Y1_N7
--operation mode is normal

B1_TEMP[15]_carry_eqn = (!B1L51 & B1L22) # (B1L51 & B1L32);
B1_TEMP[15]_lut_out = B1_TEMP[15] $ (B1_TEMP[15]_carry_eqn $ M[7]);
B1_TEMP[15] = DFFEAS(B1_TEMP[15]_lut_out, GLOBAL(CLK), !GLOBAL(RESET), , EN, , , , );


--~GND is ~GND at LC_X12_Y2_N2
--operation mode is normal

~GND = GND;


--CLK is CLK at PIN_93
--operation mode is input

CLK = INPUT();


--M[0] is M[0] at PIN_1
--operation mode is input

M[0] = INPUT();


--RESET is RESET at PIN_35
--operation mode is input

RESET = INPUT();


--EN is EN at PIN_36
--operation mode is input

EN = INPUT();


--M[1] is M[1] at PIN_2
--operation mode is input

M[1] = INPUT();


--M[2] is M[2] at PIN_3
--operation mode is input

M[2] = INPUT();


--M[3] is M[3] at PIN_4
--operation mode is input

M[3] = INPUT();


--M[4] is M[4] at PIN_5
--operation mode is input

M[4] = INPUT();


--M[5] is M[5] at PIN_6
--operation mode is input

M[5] = INPUT();


--M[6] is M[6] at PIN_7
--operation mode is input

M[6] = INPUT();


--M[7] is M[7] at PIN_10
--operation mode is input

M[7] = INPUT();


--Q[0] is Q[0] at PIN_51
--operation mode is output

Q[0] = OUTPUT(E1_q_a[0]);


--Q[1] is Q[1] at PIN_52
--operation mode is output

Q[1] = OUTPUT(E1_q_a[1]);


--Q[2] is Q[2] at PIN_67
--operation mode is output

Q[2] = OUTPUT(E1_q_a[2]);


--Q[3] is Q[3] at PIN_68
--operation mode is output

Q[3] = OUTPUT(E1_q_a[3]);


--Q[4] is Q[4] at PIN_69
--operation mode is output

Q[4] = OUTPUT(E1_q_a[4]);


--Q[5] is Q[5] at PIN_70
--operation mode is output

Q[5] = OUTPUT(E1_q_a[5]);


--Q[6] is Q[6] at PIN_71
--operation mode is output

Q[6] = OUTPUT(E1_q_a[6]);


--Q[7] is Q[7] at PIN_72
--operation mode is output

Q[7] = OUTPUT(E1_q_a[7]);