dds.tan.rpt

实现DDS频率可调得VHDL程序

; N/A           ; None        ; -7.364 ns ; M[2] ; SUM:U0|TEMP[14] ; CLK      ;
; N/A           ; None        ; -7.364 ns ; M[2] ; SUM:U0|TEMP[15] ; CLK      ;
; N/A           ; None        ; -7.397 ns ; M[1] ; SUM:U0|TEMP[11] ; CLK      ;
; N/A           ; None        ; -7.448 ns ; M[0] ; SUM:U0|TEMP[9]  ; CLK      ;
; N/A           ; None        ; -7.458 ns ; M[3] ; SUM:U0|TEMP[13] ; CLK      ;
; N/A           ; None        ; -7.458 ns ; M[3] ; SUM:U0|TEMP[14] ; CLK      ;
; N/A           ; None        ; -7.458 ns ; M[3] ; SUM:U0|TEMP[15] ; CLK      ;
; N/A           ; None        ; -7.475 ns ; M[1] ; SUM:U0|TEMP[12] ; CLK      ;
; N/A           ; None        ; -7.526 ns ; M[0] ; SUM:U0|TEMP[10] ; CLK      ;
; N/A           ; None        ; -7.604 ns ; M[0] ; SUM:U0|TEMP[11] ; CLK      ;
; N/A           ; None        ; -7.646 ns ; M[4] ; SUM:U0|TEMP[13] ; CLK      ;
; N/A           ; None        ; -7.646 ns ; M[4] ; SUM:U0|TEMP[14] ; CLK      ;
; N/A           ; None        ; -7.646 ns ; M[4] ; SUM:U0|TEMP[15] ; CLK      ;
; N/A           ; None        ; -7.682 ns ; M[0] ; SUM:U0|TEMP[12] ; CLK      ;
; N/A           ; None        ; -7.701 ns ; M[1] ; SUM:U0|TEMP[13] ; CLK      ;
; N/A           ; None        ; -7.701 ns ; M[1] ; SUM:U0|TEMP[14] ; CLK      ;
; N/A           ; None        ; -7.701 ns ; M[1] ; SUM:U0|TEMP[15] ; CLK      ;
; N/A           ; None        ; -7.912 ns ; M[0] ; SUM:U0|TEMP[13] ; CLK      ;
; N/A           ; None        ; -7.912 ns ; M[0] ; SUM:U0|TEMP[14] ; CLK      ;
; N/A           ; None        ; -7.912 ns ; M[0] ; SUM:U0|TEMP[15] ; CLK      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue May 27 18:15:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DDS -c DDS --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "SUM:U0|TEMP[9]" and destination register "SUM:U0|TEMP[15]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.271 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y1_N1; Fanout = 5; REG Node = 'SUM:U0|TEMP[9]'
            Info: 2: + IC(0.534 ns) + CELL(0.564 ns) = 1.098 ns; Loc. = LC_X15_Y1_N1; Fanout = 2; COMB Node = 'SUM:U0|TEMP[9]~77'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.176 ns; Loc. = LC_X15_Y1_N2; Fanout = 2; COMB Node = 'SUM:U0|TEMP[10]~81'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.254 ns; Loc. = LC_X15_Y1_N3; Fanout = 2; COMB Node = 'SUM:U0|TEMP[11]~85'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.432 ns; Loc. = LC_X15_Y1_N4; Fanout = 3; COMB Node = 'SUM:U0|TEMP[12]~89'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.271 ns; Loc. = LC_X15_Y1_N7; Fanout = 3; REG Node = 'SUM:U0|TEMP[15]'
            Info: Total cell delay = 1.737 ns ( 76.49 % )
            Info: Total interconnect delay = 0.534 ns ( 23.51 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.743 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'
                Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N7; Fanout = 3; REG Node = 'SUM:U0|TEMP[15]'
                Info: Total cell delay = 2.180 ns ( 79.48 % )
                Info: Total interconnect delay = 0.563 ns ( 20.52 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.743 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'
                Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N1; Fanout = 5; REG Node = 'SUM:U0|TEMP[9]'
                Info: Total cell delay = 2.180 ns ( 79.48 % )
                Info: Total interconnect delay = 0.563 ns ( 20.52 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "SUM:U0|TEMP[13]" (data pin = "M[0]", clock pin = "CLK") is 7.968 ns
    Info: + Longest pin to register delay is 10.674 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 3; PIN Node = 'M[0]'
        Info: 2: + IC(7.390 ns) + CELL(0.564 ns) = 9.423 ns; Loc. = LC_X15_Y1_N0; Fanout = 2; COMB Node = 'SUM:U0|TEMP[8]~73'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 9.501 ns; Loc. = LC_X15_Y1_N1; Fanout = 2; COMB Node = 'SUM:U0|TEMP[9]~77'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 9.579 ns; Loc. = LC_X15_Y1_N2; Fanout = 2; COMB Node = 'SUM:U0|TEMP[10]~81'
        Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 9.657 ns; Loc. = LC_X15_Y1_N3; Fanout = 2; COMB Node = 'SUM:U0|TEMP[11]~85'
        Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.835 ns; Loc. = LC_X15_Y1_N4; Fanout = 3; COMB Node = 'SUM:U0|TEMP[12]~89'
        Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 10.674 ns; Loc. = LC_X15_Y1_N5; Fanout = 5; REG Node = 'SUM:U0|TEMP[13]'
        Info: Total cell delay = 3.284 ns ( 30.77 % )
        Info: Total interconnect delay = 7.390 ns ( 69.23 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.743 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'
        Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N5; Fanout = 5; REG Node = 'SUM:U0|TEMP[13]'
        Info: Total cell delay = 2.180 ns ( 79.48 % )
        Info: Total interconnect delay = 0.563 ns ( 20.52 % )
Info: tco from clock "CLK" to destination pin "Q[4]" through memory "rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0" is 12.075 ns
    Info: + Longest clock path from clock "CLK" to source memory is 2.754 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'
        Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y2; Fanout = 4; MEM Node = 'rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0'
        Info: Total cell delay = 2.191 ns ( 79.56 % )
        Info: Total interconnect delay = 0.563 ns ( 20.44 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 8.671 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y2; Fanout = 4; MEM Node = 'rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|ram_block1a1~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y2; Fanout = 1; MEM Node = 'rom:U2|altsyncram:altsyncram_component|altsyncram_tdq:auto_generated|q_a[4]'
        Info: 3: + IC(2.255 ns) + CELL(2.108 ns) = 8.671 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'Q[4]'
        Info: Total cell delay = 6.416 ns ( 73.99 % )
        Info: Total interconnect delay = 2.255 ns ( 26.01 % )
Info: th for register "SUM:U0|TEMP[8]" (data pin = "EN", clock pin = "CLK") is -5.673 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.743 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 28; CLK Node = 'CLK'
        Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y1_N0; Fanout = 5; REG Node = 'SUM:U0|TEMP[8]'
        Info: Total cell delay = 2.180 ns ( 79.48 % )
        Info: Total interconnect delay = 0.563 ns ( 20.52 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.431 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 8; PIN Node = 'EN'
        Info: 2: + IC(6.095 ns) + CELL(0.867 ns) = 8.431 ns; Loc. = LC_X15_Y1_N0; Fanout = 5; REG Node = 'SUM:U0|TEMP[8]'
        Info: Total cell delay = 2.336 ns ( 27.71 % )
        Info: Total interconnect delay = 6.095 ns ( 72.29 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue May 27 18:15:38 2008
    Info: Elapsed time: 00:00:00