syn_frame.v

帧同步Verilog HDL源程序 实现接收机的同步功能

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:05:54 05/13/2008 
// Design Name: 
// Module Name:    syn_frame 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module syn_frame(
input		din_bit,
input		clk_bit,
input		rst_n,

output	reg	dout_bit,
output	reg	syn_out	
);

reg	[1:0] state;
reg	[7:0]	din_buf;
//reg			syn_out;
//counter
reg	[2:0]	counter_bit;
reg	[7:0]	counter_byte;
//reg	[2:0]	counter_frame;
//dout_bit
always@(posedge clk_bit or negedge rst_n)
begin
	if(!rst_n)
		begin
			dout_bit <= 1'd0;
			din_buf <= 8'd0;
		end
	else
		begin
			dout_bit <= din_buf[7];
			din_buf <= {din_buf[6:0],din_bit};
		end
end
//counter
always@(posedge clk_bit or negedge rst_n)
begin
	if(!rst_n)
		begin
			counter_bit <= 3'd0;
			counter_byte <= 8'd0;
		end
	else	if((state==2'd0)&&(din_buf==8'h47 || din_buf==8'hb8))
		begin
			counter_bit <= 3'd0;
			counter_byte <= 8'd0;
		end
	else	if(counter_bit==3'd7)
		begin
			counter_bit <= counter_bit + 3'd1;
			counter_byte <= counter_byte + 8'd1;
		end
	else
		begin
			counter_bit <= counter_bit + 3'd1;
			counter_byte <= counter_byte;			
		end	
end
//state
always@(posedge clk_bit or negedge rst_n)
begin
	if(!rst_n)
		begin
			syn_out <= 1'd0;
			state	<= 2'd0;
		end
	else	case(state)
		2'd0:
			begin
				syn_out <= 1'd0;
				if(din_buf==8'h47 || din_buf==8'hb8)
					state <= 2'd1;
				else
					state <= 2'd0;
			end
		2'd1:
			begin	
				syn_out <= 1'd0;
				if((din_buf==8'h47||din_buf==8'hb8)&&(counter_bit==3'd7)
					&&(counter_byte==8'd203))
					begin
						state <= 2'd2;
					end
				else	if((counter_bit==3'd7)&&(counter_byte==8'd203))
					begin
						state <= 2'd0;
					end
				else
					begin
						state <= 2'd1;
					end
			end
		2'd2:
			begin
				if((din_buf==8'h47||din_buf==8'hb8)&&(counter_bit==3'd7)
					&&(counter_byte==8'd203))
					begin
						state <= 2'd3;
						syn_out <= 1'd1;
					end
				else	if((counter_bit==3'd7)&&(counter_byte==8'd203))
					begin
						state <= 2'd0;
						syn_out <= 1'd0;
					end
				else
					begin
						state <= 2'd2;
						syn_out <= 1'd0;
					end		
			end
		2'd3:
			begin
				if((din_buf==8'h47||din_buf==8'hb8)&&(counter_bit==3'd7)
					&&(counter_byte==8'd203))
					begin
						state <= 2'd3;
						syn_out <= 1'd1;
					end
				else	if((counter_bit==3'd7)&&(counter_byte==8'd203))
					begin
						state <= 2'd0;
						syn_out <= 1'd0;
					end
				else	if(counter_bit==3'd7)	//keep syn_out for 1 byte
					begin
						state <= 2'd3;
						syn_out <= 1'd0;
					end
				else
					begin
						state <= 2'd3;
						syn_out <= syn_out;
					end		
			end		
		default:
			begin
				state <= 2'd0;
				syn_out <= 1'd0;
			end
		endcase	
end
endmodule