i2c.h

80c51F020的开发程序 包括ADC DDS DAC

/* ------------------------------------------------------------
	File Name: 		i2c.h
	Auther:			Samuel
	Revision:		R1
	History:		R1			Jul.05, 2007		Creation
------------------------------------------------------------ */


/* define to prevent recursive inclusion */
#ifndef __I2C_H
#define __I2C_H


/* includes --------------------------------------------------------------- */
#include <c8051f020.h>
#include "common.h"
/* types ------------------------------------------------------------------ */
#define WRITE 0x00                  // SMBus WRITE command
#define READ  0x01                  // SMBus READ command

// Device addresses (7 bits, lsb is a don't care)
#define CHIP_A 0xA0                 // Device address for chip A
#define CHIP_B 0xA2                 // Device address for chip B
#define CHIP_C 0xA4                 // Device address for chip C

// SMBus states:
// MT = Master Transmitter
// MR = Master Receiver
#define  SMB_BUS_ERROR  0x00        // (all modes) BUS ERROR
#define  SMB_START      0x08        // (MT & MR) START transmitted
#define  SMB_RP_START   0x10        // (MT & MR) repeated START
#define  SMB_MTADDACK   0x18        // (MT) Slave address + W transmitted;
                                    //  ACK received
#define  SMB_MTADDNACK  0x20        // (MT) Slave address + W transmitted;
                                    //  NACK received
#define  SMB_MTDBACK    0x28        // (MT) data byte transmitted; ACK rec'vd
#define  SMB_MTDBNACK   0x30        // (MT) data byte transmitted; NACK rec'vd
#define  SMB_MTARBLOST  0x38        // (MT) arbitration lost
#define  SMB_MRADDACK   0x40        // (MR) Slave address + R transmitted;
                                    //  ACK received
#define  SMB_MRADDNACK  0x48        // (MR) Slave address + R transmitted;
                                    //  NACK received
#define  SMB_MRDBACK    0x50        // (MR) data byte rec'vd; ACK transmitted
#define  SMB_MRDBNACK   0x58        // (MR) data byte rec'vd; NACK transmitted

typedef enum
{
	EEPROM,/* 16bit Address EEPROM(M24C32/64/128/256/512) */
	TEA5777,
	MT2060,
	TDA9886
}
I2C_Device_t;


char COMMAND;                       // Holds the slave address + R/W bit for
                                    // use in the SMBus ISR.

char WORD;                          // Holds data to be transmitted by the SMBus
                                    // OR data that has just been received.

char BYTE_NUMBER;                   // Used by ISR to check what data has just been
                                    // sent - High address byte, Low byte, or data
                                    // byte

unsigned char HIGH_ADD, LOW_ADD;    // High & Low byte for EEPROM memory address

bit SM_BUSY;                        // This bit is set when a send or receive
                                    // is started. It is cleared by the
                                    // ISR when the operation is finished.
bit temp;

I2C_Device_t I2C_Device;

/*unsigned char TEA5777_send_buffer[]={0x07,0xBF,0x09,0x04,0x00,0x00};*/
unsigned char TEA5777_send_buffer[]={0x08,0x2F,0x09,0x04,0x00,0x00};
unsigned char TEA5777_receive_buffer[3];

unsigned char *point;

long result; 

/* functions -------------------------------------------------------------- */
void EEPROM_Send (char chip_select, unsigned int byte_address, char out_byte);
char EEPROM_Receive (char chip_select, unsigned int byte_address);
void TEA5777_Send (void);
void TEA5777_Receive (void);
/* ---------- top level core functions ---------- */


/* ---------- support functions ---------- */

#endif	/* __I2C_H */

/* End of i2c.h */