transmitter.tan.qmsg

自定义编码的红外发射器

{ "Info" "ITDB_TH_RESULT" "key_boar_in:inst1\|key_data3\[9\] key_in\[9\] clk 4.500 ns register " "Info: th for register \"key_boar_in:inst1\|key_data3\[9\]\" (data pin = \"key_in\[9\]\", clock pin = \"clk\") is 4.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\] 2 REG LC5_B20 55 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC5_B20; Fanout = 55; REG Node = 'clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(0.000 ns) 10.600 ns key_boar_in:inst1\|key_data3\[9\] 3 REG LC5_E13 2 " "Info: 3: + IC(4.200 ns) + CELL(0.000 ns) = 10.600 ns; Loc. = LC5_E13; Fanout = 2; REG Node = 'key_boar_in:inst1\|key_data3\[9\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.79 % ) " "Info: Total cell delay = 3.900 ns ( 36.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 63.21 % ) " "Info: Total interconnect delay = 6.700 ns ( 63.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "10.600 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|key_data3[9] } { 0.000ns 0.000ns 2.500ns 4.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns key_in\[9\] 1 PIN PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_83; Fanout = 4; PIN Node = 'key_in\[9\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_in[9] } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 112 -112 56 128 "key_in\[12..1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.200 ns) 7.700 ns key_boar_in:inst1\|key_data3\[9\] 2 REG LC5_E13 2 " "Info: 2: + IC(3.000 ns) + CELL(1.200 ns) = 7.700 ns; Loc. = LC5_E13; Fanout = 2; REG Node = 'key_boar_in:inst1\|key_data3\[9\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { key_in[9] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns ( 61.04 % ) " "Info: Total cell delay = 4.700 ns ( 61.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 38.96 % ) " "Info: Total interconnect delay = 3.000 ns ( 38.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { key_in[9] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { key_in[9] key_in[9]~out key_boar_in:inst1|key_data3[9] } { 0.000ns 0.000ns 3.000ns } { 0.000ns 3.500ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "10.600 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|key_data3[9] } { 0.000ns 0.000ns 2.500ns 4.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { key_in[9] key_boar_in:inst1|key_data3[9] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "7.700 ns" { key_in[9] key_in[9]~out key_boar_in:inst1|key_data3[9] } { 0.000ns 0.000ns 3.000ns } { 0.000ns 3.500ns 1.200ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 08 17:16:13 2006 " "Info: Processing ended: Fri Dec 08 17:16:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}