transmitter.tan.qmsg

自定义编码的红外发射器

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_boar_in:inst1\|ready code:inst\|d\[13\] clk 900 ps " "Info: Found hold time violation between source  pin or register \"key_boar_in:inst1\|ready\" and destination pin or register \"code:inst\|d\[13\]\" for clock \"clk\" (Hold time is 900 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.600 ns + Largest " "Info: + Largest clock skew is 4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[12\] 2 REG LC8_B18 5 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC8_B18; Fanout = 5; REG Node = 'clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[12\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 10.400 ns clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~0 3 COMB LC1_B23 56 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 10.400 ns; Loc. = LC1_B23; Fanout = 56; COMB Node = 'clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~0'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.000 ns) 15.200 ns code:inst\|d\[13\] 4 REG LC8_F21 3 " "Info: 4: + IC(4.800 ns) + CELL(0.000 ns) = 15.200 ns; Loc. = LC8_F21; Fanout = 3; REG Node = 'code:inst\|d\[13\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.800 ns" { clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } "NODE_NAME" } } { "code.vhd" "" { Text "D:/01_transmitter/code.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 37.50 % ) " "Info: Total cell delay = 5.700 ns ( 37.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.500 ns ( 62.50 % ) " "Info: Total interconnect delay = 9.500 ns ( 62.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.200 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "15.200 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } { 0.000ns 0.000ns 2.500ns 2.200ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\] 2 REG LC5_B20 55 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC5_B20; Fanout = 55; REG Node = 'clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(0.000 ns) 10.600 ns key_boar_in:inst1\|ready 3 REG LC7_F19 27 " "Info: 3: + IC(4.200 ns) + CELL(0.000 ns) = 10.600 ns; Loc. = LC7_F19; Fanout = 27; REG Node = 'key_boar_in:inst1\|ready'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } "NODE_NAME" } } { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.79 % ) " "Info: Total cell delay = 3.900 ns ( 36.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 63.21 % ) " "Info: Total interconnect delay = 6.700 ns ( 63.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "10.600 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } { 0.000ns 0.000ns 2.500ns 4.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.200 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "15.200 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } { 0.000ns 0.000ns 2.500ns 2.200ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.800ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "10.600 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } { 0.000ns 0.000ns 2.500ns 4.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.200 ns - Shortest register register " "Info: - Shortest register to register delay is 4.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_boar_in:inst1\|ready 1 REG LC7_F19 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_F19; Fanout = 27; REG Node = 'key_boar_in:inst1\|ready'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_boar_in:inst1|ready } "NODE_NAME" } } { "key_boar_in.vhd" "" { Text "D:/01_transmitter/key_boar_in.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.200 ns) 4.200 ns code:inst\|d\[13\] 2 REG LC8_F21 3 " "Info: 2: + IC(3.000 ns) + CELL(1.200 ns) = 4.200 ns; Loc. = LC8_F21; Fanout = 3; REG Node = 'code:inst\|d\[13\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { key_boar_in:inst1|ready code:inst|d[13] } "NODE_NAME" } } { "code.vhd" "" { Text "D:/01_transmitter/code.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 28.57 % ) " "Info: Total cell delay = 1.200 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 3.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { key_boar_in:inst1|ready code:inst|d[13] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "4.200 ns" { key_boar_in:inst1|ready code:inst|d[13] } { 0.000ns 3.000ns } { 0.000ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "code.vhd" "" { Text "D:/01_transmitter/code.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.200 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "15.200 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12] clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~0 code:inst|d[13] } { 0.000ns 0.000ns 2.500ns 2.200ns 4.800ns } { 0.000ns 2.800ns 1.100ns 1.800ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "10.600 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] key_boar_in:inst1|ready } { 0.000ns 0.000ns 2.500ns 4.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.200 ns" { key_boar_in:inst1|ready code:inst|d[13] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "4.200 ns" { key_boar_in:inst1|ready code:inst|d[13] } { 0.000ns 3.000ns } { 0.000ns 1.200ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] fre_set\[4\] clk 20.600 ns register " "Info: tsu for register \"clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]\" (data pin = \"fre_set\[4\]\", clock pin = \"clk\") is 20.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.400 ns + Longest pin register " "Info: + Longest pin to register delay is 23.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns fre_set\[4\] 1 PIN PIN_33 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_33; Fanout = 2; PIN Node = 'fre_set\[4\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fre_set[4] } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 48 -168 0 64 "fre_set\[5..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.300 ns) + CELL(2.300 ns) 12.100 ns clk_generate:inst15\|LessThan0~319 2 COMB LC1_D14 2 " "Info: 2: + IC(6.300 ns) + CELL(2.300 ns) = 12.100 ns; Loc. = LC1_D14; Fanout = 2; COMB Node = 'clk_generate:inst15\|LessThan0~319'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.600 ns" { fre_set[4] clk_generate:inst15|LessThan0~319 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 16.600 ns clk_generate:inst15\|Equal0~30 3 COMB LC2_D13 2 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 16.600 ns; Loc. = LC2_D13; Fanout = 2; COMB Node = 'clk_generate:inst15\|Equal0~30'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 19.500 ns clk_generate:inst15\|LessThan0~324 4 COMB LC1_D13 7 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 19.500 ns; Loc. = LC1_D13; Fanout = 7; COMB Node = 'clk_generate:inst15\|LessThan0~324'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { clk_generate:inst15|Equal0~30 clk_generate:inst15|LessThan0~324 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 23.400 ns clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] 5 REG LC8_D14 3 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 23.400 ns; Loc. = LC8_D14; Fanout = 3; REG Node = 'clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk_generate:inst15|LessThan0~324 clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns ( 51.71 % ) " "Info: Total cell delay = 12.100 ns ( 51.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.300 ns ( 48.29 % ) " "Info: Total interconnect delay = 11.300 ns ( 48.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "23.400 ns" { fre_set[4] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|LessThan0~324 clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "23.400 ns" { fre_set[4] fre_set[4]~out clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|LessThan0~324 clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 6.300ns 2.200ns 0.600ns 2.200ns } { 0.000ns 3.500ns 2.300ns 2.300ns 2.300ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC8_D14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_D14; Fanout = 3; REG Node = 'clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "23.400 ns" { fre_set[4] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|LessThan0~324 clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "23.400 ns" { fre_set[4] fre_set[4]~out clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|LessThan0~324 clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 6.300ns 2.200ns 0.600ns 2.200ns } { 0.000ns 3.500ns 2.300ns 2.300ns 2.300ns 1.700ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk key_clk inst13 26.600 ns register " "Info: tco from clock \"clk\" to destination pin \"key_clk\" through register \"inst13\" is 26.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 16.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\] 2 REG LC5_B20 55 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC5_B20; Fanout = 55; REG Node = 'clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.100 ns) 10.700 ns inst5 3 REG LC2_C16 2 " "Info: 3: + IC(3.200 ns) + CELL(1.100 ns) = 10.700 ns; Loc. = LC2_C16; Fanout = 2; REG Node = 'inst5'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.300 ns" { clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] inst5 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -232 488 552 -152 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.100 ns) 12.400 ns inst9 4 REG LC1_C16 3 " "Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 12.400 ns; Loc. = LC1_C16; Fanout = 3; REG Node = 'inst9'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { inst5 inst9 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 712 776 -168 "inst9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.100 ns) 15.700 ns inst11 5 REG LC3_C21 3 " "Info: 5: + IC(2.200 ns) + CELL(1.100 ns) = 15.700 ns; Loc. = LC3_C21; Fanout = 3; REG Node = 'inst11'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { inst9 inst11 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 888 952 -168 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 16.300 ns inst13 6 REG LC2_C21 2 " "Info: 6: + IC(0.600 ns) + CELL(0.000 ns) = 16.300 ns; Loc. = LC2_C21; Fanout = 2; REG Node = 'inst13'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.600 ns" { inst11 inst13 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 1064 1128 -168 "inst13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 44.17 % ) " "Info: Total cell delay = 7.200 ns ( 44.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.100 ns ( 55.83 % ) " "Info: Total interconnect delay = 9.100 ns ( 55.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.300 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] inst5 inst9 inst11 inst13 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "16.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] inst5 inst9 inst11 inst13 } { 0.000ns 0.000ns 2.500ns 3.200ns 0.600ns 2.200ns 0.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 1064 1128 -168 "inst13" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.200 ns + Longest register pin " "Info: + Longest register to pin delay is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst13 1 REG LC2_C21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C21; Fanout = 2; REG Node = 'inst13'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inst13 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 1064 1128 -168 "inst13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns inst4~20 2 COMB LC1_C21 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_C21; Fanout = 1; COMB Node = 'inst4~20'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { inst13 inst4~20 } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -120 1160 1224 -72 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(5.100 ns) 9.200 ns key_clk 3 PIN PIN_138 0 " "Info: 3: + IC(1.200 ns) + CELL(5.100 ns) = 9.200 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'key_clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { inst4~20 key_clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -104 1296 1472 -88 "key_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 80.43 % ) " "Info: Total cell delay = 7.400 ns ( 80.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 19.57 % ) " "Info: Total interconnect delay = 1.800 ns ( 19.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { inst13 inst4~20 key_clk } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { inst13 inst4~20 key_clk } { 0.000ns 0.600ns 1.200ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.300 ns" { clk clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] inst5 inst9 inst11 inst13 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "16.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[17] inst5 inst9 inst11 inst13 } { 0.000ns 0.000ns 2.500ns 3.200ns 0.600ns 2.200ns 0.600ns } { 0.000ns 2.800ns 1.100ns 1.100ns 1.100ns 1.100ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.200 ns" { inst13 inst4~20 key_clk } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "9.200 ns" { inst13 inst4~20 key_clk } { 0.000ns 0.600ns 1.200ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}