transmitter.tan.qmsg

自定义编码的红外发射器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\] " "Info: Detected ripple clock \"clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "d:/program_files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program_files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inst5 " "Info: Detected ripple clock \"inst5\" as buffer" {  } { { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -232 488 552 -152 "inst5" "" } } } } { "d:/program_files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program_files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inst9 " "Info: Detected ripple clock \"inst9\" as buffer" {  } { { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 712 776 -168 "inst9" "" } } } } { "d:/program_files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program_files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "inst11 " "Info: Detected ripple clock \"inst11\" as buffer" {  } { { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { -248 888 952 -168 "inst11" "" } } } } { "d:/program_files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program_files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst11" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[12\] " "Info: Detected ripple clock \"clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[12\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "d:/program_files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program_files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_generate:inst15\|lpm_counter:count_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] register clk_generate:inst15\|D 31.85 MHz 31.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 31.85 MHz between source register \"clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]\" and destination register \"clk_generate:inst15\|D\" (period= 31.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.100 ns + Longest register register " "Info: + Longest register to register delay is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] 1 REG LC8_D14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_D14; Fanout = 3; REG Node = 'clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns clk_generate:inst15\|LessThan0~319 2 COMB LC1_D14 2 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_D14; Fanout = 2; COMB Node = 'clk_generate:inst15\|LessThan0~319'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] clk_generate:inst15|LessThan0~319 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 7.400 ns clk_generate:inst15\|Equal0~30 3 COMB LC2_D13 2 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 7.400 ns; Loc. = LC2_D13; Fanout = 2; COMB Node = 'clk_generate:inst15\|Equal0~30'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 10.300 ns clk_generate:inst15\|Equal0~32 4 COMB LC3_D13 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 10.300 ns; Loc. = LC3_D13; Fanout = 1; COMB Node = 'clk_generate:inst15\|Equal0~32'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { clk_generate:inst15|Equal0~30 clk_generate:inst15|Equal0~32 } "NODE_NAME" } } { "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program_files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 12.100 ns clk_generate:inst15\|D 5 REG LC8_D13 9 " "Info: 5: + IC(0.600 ns) + CELL(1.200 ns) = 12.100 ns; Loc. = LC8_D13; Fanout = 9; REG Node = 'clk_generate:inst15\|D'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { clk_generate:inst15|Equal0~32 clk_generate:inst15|D } "NODE_NAME" } } { "clk_generate.vhd" "" { Text "D:/01_transmitter/clk_generate.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns ( 66.94 % ) " "Info: Total cell delay = 8.100 ns ( 66.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 33.06 % ) " "Info: Total interconnect delay = 4.000 ns ( 33.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.100 ns" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|Equal0~32 clk_generate:inst15|D } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "12.100 ns" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|Equal0~32 clk_generate:inst15|D } { 0.000ns 0.600ns 2.200ns 0.600ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns clk_generate:inst15\|D 2 REG LC8_D13 9 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_D13; Fanout = 9; REG Node = 'clk_generate:inst15\|D'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk_generate:inst15|D } "NODE_NAME" } } { "clk_generate.vhd" "" { Text "D:/01_transmitter/clk_generate.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|D } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|D } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 34; CLK Node = 'clk'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "transmitter.bdf" "" { Schematic "D:/01_transmitter/transmitter.bdf" { { 16 -160 8 32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC8_D14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_D14; Fanout = 3; REG Node = 'clk_generate:inst15\|lpm_counter:temp_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|D } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|D } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "clk_generate.vhd" "" { Text "D:/01_transmitter/clk_generate.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } { "clk_generate.vhd" "" { Text "D:/01_transmitter/clk_generate.vhd" 51 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.100 ns" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|Equal0~32 clk_generate:inst15|D } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "12.100 ns" { clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] clk_generate:inst15|LessThan0~319 clk_generate:inst15|Equal0~30 clk_generate:inst15|Equal0~32 clk_generate:inst15|D } { 0.000ns 0.600ns 2.200ns 0.600ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.200ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|D } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|D } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program_files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { clk clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program_files/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { clk clk~out clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}