📄 key_boar_in.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY key_boar_in IS
PORT (clk_key,reset: IN STD_LOGIC;
key_in: in STD_LOGIC_VECTOR(12 DOWNTO 1);
key_out: out STD_LOGIC_VECTOR(12 DOWNTO 1) ;
ready: out std_logic
);
END ENTITY key_boar_in;
ARCHITECTURE arc of key_boar_in IS
signal count: STD_LOGIC_VECTOR(2 DOWNTO 0);
signal key_data1, key_data2,key_data3: std_logic_vector(12 downto 1);
signal clk_drv: std_logic;
BEGIN
aa:PROCESS(clk_key,reset,key_in,count,key_data1,key_data2,key_data3) --- eliminate jitter
BEGIN
IF reset='1' THEN
key_data1<="000000000000";
key_data2<="000000000000";
key_data3<="000000000000";
else
if clk_key'event and clk_key='0' then --- 3 times dectec key board
case count is
when "001" => key_data1<=key_in;
when "011" => key_data2<=key_in;
when "101" => key_data3<=key_in;
when others =>null;
end case;
end if;
end if;
end process aa;
bb: process(clk_key, key_data1,key_in,count,key_data2,key_data3)
begin
if clk_key'event and clk_key='0' then
if ( count="111" and key_in /= "111111111111" ) then
if key_data1 = key_data3 and key_data2=key_data3 then
key_out<=key_data2;
ready<='1';
end if;
else
key_out<="000000000000" ;
ready<='0';
end if;
end if;
end process bb;
cc: process (clk_key ,count,reset)
begin
if reset='1' then
count<="000";
else
if clk_key'event and clk_key='1' then
count<=count+1;
end if;
end if;
end process cc;
end arc;
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