transmitter.tan.rpt

自定义编码的红外发射器

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K20TC144-4    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                           ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 31.85 MHz ( period = 31.400 ns )                    ; clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5] ; clk_generate:inst15|D         ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 31.85 MHz ( period = 31.400 ns )                    ; clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[4] ; clk_generate:inst15|D         ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[1]                                                   ; code:inst|d[5]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[5]                                                   ; code:inst|d[5]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[4]                                                   ; code:inst|d[5]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[1]                                                   ; code:inst|d[0]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[5]                                                   ; code:inst|d[0]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.15 MHz ( period = 31.100 ns )                    ; key_boar_in:inst1|key_out[4]                                                   ; code:inst|d[0]                ; clk        ; clk      ; None                        ; None                      ; 31.900 ns               ;
; N/A                                     ; 32.68 MHz ( period = 30.600 ns )                    ; key_boar_in:inst1|key_out[6]                                                   ; code:inst|d[5]                ; clk        ; clk      ; None                        ; None                      ; 31.400 ns               ;
; N/A                                     ; 32.68 MHz ( period = 30.600 ns )                    ; key_boar_in:inst1|key_out[6]                                                   ; code:inst|d[0]                ; clk        ; clk      ; None                        ; None                      ; 31.400 ns               ;
; N/A                                     ; 32.89 MHz ( period = 30.400 ns )                    ; key_boar_in:inst1|count[2]                                                     ; key_boar_in:inst1|key_out[2]  ; clk        ; clk      ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 32.89 MHz ( period = 30.400 ns )                    ; key_boar_in:inst1|count[0]                                                     ; key_boar_in:inst1|key_out[2]  ; clk        ; clk      ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 32.89 MHz ( period = 30.400 ns )                    ; key_boar_in:inst1|count[1]                                                     ; key_boar_in:inst1|key_out[2]  ; clk        ; clk      ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 33.11 MHz ( period = 30.200 ns )                    ; key_boar_in:inst1|count[2]                                                     ; key_boar_in:inst1|key_out[11] ; clk        ; clk      ; None                        ; None                      ; 11.700 ns               ;