clk_generate.vhd

自定义编码的红外发射器

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  clk_generate  IS
PORT        (clk, reset: IN STD_LOGIC;        --  clk in 4.096MHz
             clk_key,clk_send,osc: out STD_LOGIC; --- clk_key div 13 , clk_send div 20 ,osc div 111
              fre_set: in std_logic_vector(5 downto 0) );
END  ENTITY clk_generate;
ARCHITECTURE arch of clk_generate  IS
signal count: std_logic_vector(19 downto 0);
signal temp : std_logic_vector(5 downto 0);
signal D:   std_logic;

BEGIN
   clk_send <= count(12);  -- code send clk generate count(12)
   clk_key  <= count(17);  -- key board detect clk count(18)
   osc<=D;                 -- carry wave osc
aa:PROCESS(clk,reset,count) 
   BEGIN 
  if reset='1' then 
     count<="00000000000000000000";
   else 
    if clk'event and clk = '1' then
       count <= count+1;
    end if;
  end if;
  end process aa;


bb: process(reset,clk,temp,fre_set)
    begin
    if reset='1' then
     temp<="000000";
    else 
    
      if clk'event and clk ='1' then
         if temp < fre_set then
            temp<=temp+1;
         else
           temp<="000000";
           
         end if;
       end if;
     end if;
    end process bb;
cc: process(clk,temp,reset,D,fre_set)
    begin
    if reset='1' then
     D<='0';
    else
         if clk'event and clk='0' then
           if temp= fre_set then
            D<=not(D);
            end if;
         end if;
    end if;
    end process cc;
 end arch;