transmitter.sim.rpt

自定义编码的红外发射器

; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      24.08 % ;
; Total nodes checked                                 ; 196          ;
; Total output ports checked                          ; 191          ;
; Total output ports with complete 1/0-value coverage ; 46           ;
; Total output ports with no 1/0-value coverage       ; 143          ;
; Total output ports with no 1-value coverage         ; 145          ;
; Total output ports with no 0-value coverage         ; 143          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                    ;
+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                    ; Output Port Name                                                                                             ; Output Port Type ;
+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------+
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12]                 ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12]                 ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|q[12]                 ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[2]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[2]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[2]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT   ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[3]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[3]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[3]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT   ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[1]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[1]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[1]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT   ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[0]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[0]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[0]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT   ; cout             ;
; |transmitter|clk_generate:inst2|Equal0~38                                                                    ; |transmitter|clk_generate:inst2|Equal0~38                                                                    ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[5]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[4]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[4]                   ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|q[4]                   ; |transmitter|clk_generate:inst2|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT   ; cout             ;
; |transmitter|clk_generate:inst2|Equal0~39                                                                    ; |transmitter|clk_generate:inst2|Equal0~39                                                                    ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|Equal0~40                                                                    ; |transmitter|clk_generate:inst2|Equal0~40                                                                    ; data_out0        ;
; |transmitter|clk_generate:inst2|LessThan0~40                                                                 ; |transmitter|clk_generate:inst2|LessThan0~40                                                                 ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT ; cout             ;
; |transmitter|key_boar_in:inst1|Equal1~73                                                                     ; |transmitter|key_boar_in:inst1|Equal1~73                                                                     ; cascout          ;
; |transmitter|key_boar_in:inst1|Equal1~70                                                                     ; |transmitter|key_boar_in:inst1|Equal1~70                                                                     ; data_out0        ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT  ; cout             ;
; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT  ; |transmitter|clk_generate:inst2|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT  ; cout             ;