📄 transmitter.map.rpt
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------+
; |transmitter ; 221 (5) ; 141 ; 0 ; 34 ; 80 (1) ; 33 (0) ; 108 (4) ; 24 (0) ; 0 (0) ; |transmitter ;
; |LED_SET:inst8| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |transmitter|LED_SET:inst8 ;
; |clk_generate:inst15| ; 34 (10) ; 25 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 25 (1) ; 24 (0) ; 0 (0) ; |transmitter|clk_generate:inst15 ;
; |lpm_counter:count_rtl_0| ; 18 (0) ; 18 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 18 (0) ; 18 (0) ; 0 (0) ; |transmitter|clk_generate:inst15|lpm_counter:count_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 18 (18) ; 18 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 18 (18) ; 18 (18) ; 0 (0) ; |transmitter|clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter ;
; |lpm_counter:temp_rtl_1| ; 6 (0) ; 6 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (0) ; 6 (0) ; 0 (0) ; |transmitter|clk_generate:inst15|lpm_counter:temp_rtl_1 ;
; |alt_counter_f10ke:wysi_counter| ; 6 (6) ; 6 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 6 (6) ; 0 (0) ; |transmitter|clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter ;
; |code:inst| ; 103 (103) ; 56 ; 0 ; 0 ; 47 (47) ; 33 (33) ; 23 (23) ; 0 (0) ; 0 (0) ; |transmitter|code:inst ;
; |key_boar_in:inst1| ; 75 (75) ; 52 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 52 (52) ; 0 (0) ; 0 (0) ; |transmitter|key_boar_in:inst1 ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 141 ;
; Number of registers using Synchronous Clear ; 6 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 120 ;
; Number of registers using Asynchronous Load ; 28 ;
; Number of registers using Clock Enable ; 59 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clk_generate:inst15|lpm_counter:count_rtl_0 ;
+------------------------+-------------------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 20 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: clk_generate:inst15|lpm_counter:temp_rtl_1 ;
+------------------------+-------------------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 6 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Dec 08 17:15:51 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off transmitter -c transmitter
Info: Found 2 design units, including 1 entities, in source file clk_generate.vhd
Info: Found design unit 1: clk_generate-arch
Info: Found entity 1: clk_generate
Info: Found 2 design units, including 1 entities, in source file code.vhd
Info: Found design unit 1: code-send
Info: Found entity 1: code
Info: Found 2 design units, including 1 entities, in source file key_boar_in.vhd
Info: Found design unit 1: key_boar_in-arc
Info: Found entity 1: key_boar_in
Info: Found 1 design units, including 1 entities, in source file transmitter.bdf
Info: Found entity 1: transmitter
Info: Found 2 design units, including 1 entities, in source file LED_SET.vhdl
Info: Found design unit 1: LED_set-archt
Info: Found entity 1: LED_SET
Info: Elaborating entity "transmitter" for the top level hierarchy
Info: Elaborating entity "key_boar_in" for hierarchy "key_boar_in:inst1"
Info: Elaborating entity "clk_generate" for hierarchy "clk_generate:inst15"
Info: Elaborating entity "LED_SET" for hierarchy "LED_SET:inst8"
Info: Elaborating entity "code" for hierarchy "code:inst"
Warning: Reduced register "code:inst|temp[1]" with stuck data_in port to stuck value GND
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=20) from the following logic: "clk_generate:inst15|count[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "clk_generate:inst15|temp[0]~6"
Info: Found 1 design units, including 1 entities, in source file ../program_files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "clk_generate:inst15|lpm_counter:count_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../program_files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "clk_generate:inst15|lpm_counter:count_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "clk_generate:inst15|lpm_counter:count_rtl_0"
Info: Instantiated megafunction "clk_generate:inst15|lpm_counter:count_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "20"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "clk_generate:inst15|lpm_counter:temp_rtl_1"
Info: Elaborated megafunction instantiation "clk_generate:inst15|lpm_counter:temp_rtl_1|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "clk_generate:inst15|lpm_counter:temp_rtl_1"
Info: Instantiated megafunction "clk_generate:inst15|lpm_counter:temp_rtl_1" with the following parameter:
Info: Parameter "LPM_WIDTH" = "6"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Duplicate registers merged to single register
Info: Duplicate register "LED_SET:inst8|send_out[5]" merged to single register "LED_SET:inst8|send_out[6]"
Info: Duplicate register "LED_SET:inst8|send_out[2]" merged to single register "LED_SET:inst8|send_out[3]"
Info: Duplicate register "LED_SET:inst8|send_out[0]" merged to single register "LED_SET:inst8|send_out[1]"
Info: Implemented 255 device resources after synthesis - the final resource count might be different
Info: Implemented 22 input pins
Info: Implemented 12 output pins
Info: Implemented 221 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Fri Dec 08 17:15:56 2006
Info: Elapsed time: 00:00:05
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