📄 tiaojia.rpt
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02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\tiaojia.rpt
tiaojia
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 up
INPUT 2 sure
Device-Specific Information: e:\eda\tiaojia.rpt
tiaojia
** EQUATIONS **
flag1 : INPUT;
sure : INPUT;
up : INPUT;
-- Node name is ':249' = 'count10'
-- Equation name is 'count10', location is LC5_C4, type is buried.
count10 = DFFE( _EQ001, GLOBAL( sure), VCC, VCC, flag1);
_EQ001 = !count10 & !count11;
-- Node name is ':248' = 'count11'
-- Equation name is 'count11', location is LC3_C4, type is buried.
count11 = DFFE( _EQ002, GLOBAL( sure), VCC, VCC, flag1);
_EQ002 = count10 & !count11;
-- Node name is ':27' = 'data10'
-- Equation name is 'data10', location is LC7_C9, type is buried.
data10 = DFFE(!data10, GLOBAL( up), VCC, VCC, !_LC1_C4);
-- Node name is ':26' = 'data11'
-- Equation name is 'data11', location is LC3_C9, type is buried.
data11 = DFFE( _EQ003, GLOBAL( up), VCC, VCC, !_LC1_C4);
_EQ003 = !data10 & data11 & !_LC2_C9
# data10 & !data11 & !_LC2_C9;
-- Node name is ':25' = 'data12'
-- Equation name is 'data12', location is LC1_C9, type is buried.
data12 = DFFE( _EQ004, GLOBAL( up), VCC, VCC, !_LC1_C4);
_EQ004 = data12 & !_LC2_C9 & !_LC4_C9
# !data12 & !_LC2_C9 & _LC4_C9;
-- Node name is ':24' = 'data13'
-- Equation name is 'data13', location is LC5_C9, type is buried.
data13 = DFFE( _EQ005, GLOBAL( up), VCC, VCC, !_LC1_C4);
_EQ005 = data13 & !_LC2_C9 & !_LC6_C9
# !data13 & !_LC2_C9 & _LC6_C9;
-- Node name is ':103' = 'data20'
-- Equation name is 'data20', location is LC6_B12, type is buried.
data20 = DFFE(!data20, GLOBAL( up), VCC, VCC, !_LC4_C4);
-- Node name is ':102' = 'data21'
-- Equation name is 'data21', location is LC2_B12, type is buried.
data21 = DFFE( _EQ006, GLOBAL( up), VCC, VCC, !_LC4_C4);
_EQ006 = !data20 & data21 & !_LC4_B12
# data20 & !data21 & !_LC4_B12;
-- Node name is ':101' = 'data22'
-- Equation name is 'data22', location is LC1_B12, type is buried.
data22 = DFFE( _EQ007, GLOBAL( up), VCC, VCC, !_LC4_C4);
_EQ007 = data22 & !_LC4_B12 & !_LC5_B12
# !data22 & !_LC4_B12 & _LC5_B12;
-- Node name is ':100' = 'data23'
-- Equation name is 'data23', location is LC3_B12, type is buried.
data23 = DFFE( _EQ008, GLOBAL( up), VCC, VCC, !_LC4_C4);
_EQ008 = data23 & !_LC4_B12 & !_LC7_B12
# !data23 & !_LC4_B12 & _LC7_B12;
-- Node name is ':179' = 'data30'
-- Equation name is 'data30', location is LC1_C22, type is buried.
data30 = DFFE(!data30, GLOBAL( up), VCC, VCC, !_LC2_C4);
-- Node name is ':178' = 'data31'
-- Equation name is 'data31', location is LC6_C22, type is buried.
data31 = DFFE( _EQ009, GLOBAL( up), VCC, VCC, !_LC2_C4);
_EQ009 = !data30 & data31 & !_LC3_C22
# data30 & !data31 & !_LC3_C22;
-- Node name is ':177' = 'data32'
-- Equation name is 'data32', location is LC4_C22, type is buried.
data32 = DFFE( _EQ010, GLOBAL( up), VCC, VCC, !_LC2_C4);
_EQ010 = data32 & !_LC3_C22 & !_LC5_C22
# !data32 & !_LC3_C22 & _LC5_C22;
-- Node name is ':176' = 'data33'
-- Equation name is 'data33', location is LC2_C22, type is buried.
data33 = DFFE( _EQ011, GLOBAL( up), VCC, VCC, !_LC2_C4);
_EQ011 = data33 & !_LC3_C22 & !_LC7_C22
# !data33 & !_LC3_C22 & _LC7_C22;
-- Node name is 'price10'
-- Equation name is 'price10', type is output
price10 = data10;
-- Node name is 'price11'
-- Equation name is 'price11', type is output
price11 = data11;
-- Node name is 'price12'
-- Equation name is 'price12', type is output
price12 = data12;
-- Node name is 'price13'
-- Equation name is 'price13', type is output
price13 = data13;
-- Node name is 'price20'
-- Equation name is 'price20', type is output
price20 = data20;
-- Node name is 'price21'
-- Equation name is 'price21', type is output
price21 = data21;
-- Node name is 'price22'
-- Equation name is 'price22', type is output
price22 = data22;
-- Node name is 'price23'
-- Equation name is 'price23', type is output
price23 = data23;
-- Node name is 'price30'
-- Equation name is 'price30', type is output
price30 = data30;
-- Node name is 'price31'
-- Equation name is 'price31', type is output
price31 = data31;
-- Node name is 'price32'
-- Equation name is 'price32', type is output
price32 = data32;
-- Node name is 'price33'
-- Equation name is 'price33', type is output
price33 = data33;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = LCELL( _EQ012);
_EQ012 = data10 & data11;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = LCELL( _EQ013);
_EQ013 = data10 & data11 & data12;
-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ014);
_EQ014 = data20 & data21;
-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B12', type is buried
_LC7_B12 = LCELL( _EQ015);
_EQ015 = data20 & data21 & data22;
-- Node name is '|LPM_ADD_SUB:203|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ016);
_EQ016 = data30 & data31;
-- Node name is '|LPM_ADD_SUB:203|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ017);
_EQ017 = data30 & data31 & data32;
-- Node name is ':36'
-- Equation name is '_LC1_C4', type is buried
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ018);
_EQ018 = !count10 & !count11 & flag1;
-- Node name is ':42'
-- Equation name is '_LC2_C9', type is buried
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ019);
_EQ019 = data11
# !data13
# data12
# !data10;
-- Node name is ':112'
-- Equation name is '_LC4_C4', type is buried
!_LC4_C4 = _LC4_C4~NOT;
_LC4_C4~NOT = LCELL( _EQ020);
_EQ020 = count10 & !count11 & flag1;
-- Node name is ':118'
-- Equation name is '_LC4_B12', type is buried
!_LC4_B12 = _LC4_B12~NOT;
_LC4_B12~NOT = LCELL( _EQ021);
_EQ021 = data21
# !data23
# data22
# !data20;
-- Node name is ':188'
-- Equation name is '_LC2_C4', type is buried
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ022);
_EQ022 = !count10 & count11 & flag1;
-- Node name is ':194'
-- Equation name is '_LC3_C22', type is buried
!_LC3_C22 = _LC3_C22~NOT;
_LC3_C22~NOT = LCELL( _EQ023);
_EQ023 = data31
# !data33
# data32
# !data30;
Project Information e:\eda\tiaojia.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,662K
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