count24.rpt

消抖程序

-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = LCELL( _EQ005);
  _EQ005 =  count5 & !_LC6_A4
         # !count5 &  _LC6_A4;

-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:154' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ006);
  _EQ006 = !count5 &  count6
         #  count6 & !_LC6_A4
         #  count5 & !count6 &  _LC6_A4;

-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = LCELL( _EQ007);
  _EQ007 = !count5 &  count7
         #  count7 & !_LC6_A4
         # !count6 &  count7
         #  count5 &  count6 & !count7 &  _LC6_A4;

-- Node name is '|LPM_ADD_SUB:194|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_A3', type is buried 
_LC8_A3  = LCELL( _EQ008);
  _EQ008 = !_LC1_A4 &  _LC2_A3
         # !count0 &  count1 & !_LC1_A4
         #  count0 & !count1 & !_LC1_A4;

-- Node name is '|LPM_ADD_SUB:194|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A8', type is buried 
_LC3_A8  = LCELL( _EQ009);
  _EQ009 =  _LC1_A8 &  _LC4_A8 &  _LC8_A3;

-- Node name is '|LPM_ADD_SUB:194|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = LCELL( _EQ010);
  _EQ010 =  count5 &  _LC3_A8 & !_LC6_A4
         # !count5 &  _LC3_A8 &  _LC6_A4;

-- Node name is '|LPM_ADD_SUB:194|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ011);
  _EQ011 =  count5 & !count6 &  _LC5_A4 &  _LC6_A4
         # !count5 &  count6 &  _LC5_A4
         #  count6 &  _LC5_A4 & !_LC6_A4;

-- Node name is '~106~1' 
-- Equation name is '~106~1', location is LC2_A4, type is buried.
-- synthesized logic cell 
_LC2_A4  = LCELL( _EQ012);
  _EQ012 =  count6
         # !count5
         #  count7
         #  count4;

-- Node name is ':106' 
-- Equation name is '_LC1_A4', type is buried 
!_LC1_A4 = _LC1_A4~NOT;
_LC1_A4~NOT = LCELL( _EQ013);
  _EQ013 =  _LC2_A4
         #  count3
         #  count2
         # !_LC4_A2;

-- Node name is ':159' 
-- Equation name is '_LC4_A8', type is buried 
!_LC4_A8 = _LC4_A8~NOT;
_LC4_A8~NOT = LCELL( _EQ014);
  _EQ014 =  _LC1_A4
         #  count2 &  count3 &  _LC4_A2
         # !count2 & !count3
         # !count3 & !_LC4_A2;

-- Node name is ':181' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = LCELL( _EQ015);
  _EQ015 =  count0 &  count1 & !_LC2_A3
         # !count0 & !count1 & !_LC2_A3;

-- Node name is ':185' 
-- Equation name is '_LC4_A3', type is buried 
!_LC4_A3 = _LC4_A3~NOT;
_LC4_A3~NOT = LCELL( _EQ016);
  _EQ016 = !_LC4_A8
         #  count0 &  count1 & !_LC2_A3
         # !count0 & !count1 & !_LC2_A3;

-- Node name is ':204' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = LCELL( _EQ017);
  _EQ017 =  _LC4_A3 &  _LC4_A4 & !_LC7_A4
         #  _LC4_A3 & !_LC4_A4 &  _LC7_A4
         # !_LC1_A4 & !_LC4_A3 &  _LC7_A4;

-- Node name is ':210' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ018);
  _EQ018 = !_LC1_A2 &  _LC4_A3 &  _LC5_A4
         #  _LC1_A2 &  _LC4_A3 & !_LC5_A4
         #  _LC1_A2 & !_LC1_A4 & !_LC4_A3;

-- Node name is ':216' 
-- Equation name is '_LC7_A8', type is buried 
_LC7_A8  = LCELL( _EQ019);
  _EQ019 =  _LC3_A8 &  _LC4_A3 & !_LC5_A8
         # !_LC3_A8 &  _LC4_A3 &  _LC5_A8
         # !_LC1_A4 & !_LC4_A3 &  _LC5_A8;

-- Node name is ':222' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = LCELL( _EQ020);
  _EQ020 = !_LC1_A8 &  _LC4_A3 &  _LC8_A3
         #  _LC1_A8 &  _LC4_A3 & !_LC8_A3
         # !_LC1_A4 &  _LC1_A8 & !_LC4_A3;

-- Node name is ':234' 
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = LCELL( _EQ021);
  _EQ021 =  _LC5_A3
         # !_LC1_A4 &  _LC2_A3 & !_LC4_A8;

-- Node name is ':235' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ022);
  _EQ022 = !count0 &  count1 &  _LC2_A3 &  _LC4_A3
         #  count0 & !count1 &  _LC2_A3 &  _LC4_A3
         #  count0 &  count1 & !_LC2_A3 &  _LC4_A3
         # !count0 & !count1 & !_LC2_A3 &  _LC4_A3;

-- Node name is ':240' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ023);
  _EQ023 =  _LC6_A2
         #  count0 &  count1 &  _LC4_A3
         # !count0 & !count1 &  _LC4_A3;

-- Node name is ':242' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ024);
  _EQ024 = !count0 &  count1 & !_LC1_A4 & !_LC4_A8
         #  count0 & !count1 & !_LC1_A4 & !_LC4_A8;

-- Node name is '~282~1' 
-- Equation name is '~282~1', location is LC3_A3, type is buried.
-- synthesized logic cell 
_LC3_A3  = LCELL( _EQ025);
  _EQ025 =  _LC4_A8 & !_LC8_A3
         #  _LC4_A8 &  _LC7_A3;



Project Information                                         e:\eda\count24.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,350K