📄 count24.rpt
字号:
count24
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - - 02 OUTPUT 0 1 0 0 time30
70 - - A -- OUTPUT 0 1 0 0 time31
16 - - A -- OUTPUT 0 1 0 0 time32
17 - - A -- OUTPUT 0 1 0 0 time33
18 - - A -- OUTPUT 0 1 0 0 time40
19 - - A -- OUTPUT 0 1 0 0 time41
69 - - A -- OUTPUT 0 1 0 0 time42
8 - - - 03 OUTPUT 0 1 0 0 time43
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\count24.rpt
count24
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 02 OR2 ! 0 2 0 5 |LPM_ADD_SUB:123|addcore:adder|:121
- 6 - A 04 AND2 0 4 0 5 |LPM_ADD_SUB:123|addcore:adder|:133
- 2 - A 03 OR2 0 2 0 5 |LPM_ADD_SUB:123|addcore:adder|:150
- 1 - A 08 OR2 0 4 0 2 |LPM_ADD_SUB:123|addcore:adder|:152
- 5 - A 08 OR2 0 2 0 1 |LPM_ADD_SUB:123|addcore:adder|:153
- 1 - A 02 OR2 0 3 0 1 |LPM_ADD_SUB:123|addcore:adder|:154
- 7 - A 04 OR2 0 4 0 1 |LPM_ADD_SUB:123|addcore:adder|:155
- 8 - A 03 OR2 0 4 0 3 |LPM_ADD_SUB:194|addcore:adder|pcarry2
- 3 - A 08 AND2 0 3 0 2 |LPM_ADD_SUB:194|addcore:adder|:133
- 5 - A 04 OR2 0 3 0 2 |LPM_ADD_SUB:194|addcore:adder|:137
- 4 - A 04 OR2 0 4 0 1 |LPM_ADD_SUB:194|addcore:adder|:141
- 3 - A 04 DFFE + 1 1 1 2 count7 (:21)
- 7 - A 02 DFFE + 1 1 1 4 count6 (:22)
- 6 - A 08 DFFE + 1 1 1 6 count5 (:23)
- 8 - A 08 DFFE + 1 1 1 3 count4 (:24)
- 2 - A 10 DFFE + 1 1 1 4 count3 (:25)
- 1 - A 03 DFFE + 1 1 1 5 count2 (:26)
- 5 - A 02 DFFE + 1 1 1 7 count1 (:27)
- 3 - A 02 DFFE + 1 0 1 7 count0 (:28)
- 2 - A 04 OR2 s 0 4 0 1 ~106~1
- 1 - A 04 OR2 ! 0 4 0 8 :106
- 4 - A 08 OR2 ! 0 4 0 5 :159
- 7 - A 03 OR2 0 3 0 1 :181
- 4 - A 03 OR2 ! 0 4 0 6 :185
- 8 - A 04 OR2 0 4 0 1 :204
- 2 - A 02 OR2 0 4 0 1 :210
- 7 - A 08 OR2 0 4 0 1 :216
- 2 - A 08 OR2 0 4 0 1 :222
- 6 - A 03 OR2 0 4 0 1 :234
- 5 - A 03 OR2 0 4 0 1 :235
- 8 - A 02 OR2 0 4 0 1 :240
- 6 - A 02 OR2 0 4 0 1 :242
- 3 - A 03 OR2 s 0 3 0 1 ~282~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\count24.rpt
count24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 17/ 48( 35%) 0/ 48( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\count24.rpt
count24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\eda\count24.rpt
count24
** EQUATIONS **
clk : INPUT;
flag2 : INPUT;
hour10 : INPUT;
hour11 : INPUT;
hour12 : INPUT;
hour13 : INPUT;
hour20 : INPUT;
hour21 : INPUT;
hour22 : INPUT;
hour23 : INPUT;
-- Node name is ':28' = 'count0'
-- Equation name is 'count0', location is LC3_A2, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), !(GLOBAL( flag2) & !hour10), !(GLOBAL( flag2) & hour10), VCC);
-- Node name is ':27' = 'count1'
-- Equation name is 'count1', location is LC5_A2, type is buried.
count1 = DFFE( _LC8_A2, GLOBAL( clk), !(GLOBAL( flag2) & !hour11), !(GLOBAL( flag2) & hour11), VCC);
-- Node name is ':26' = 'count2'
-- Equation name is 'count2', location is LC1_A3, type is buried.
count2 = DFFE( _LC6_A3, GLOBAL( clk), !(GLOBAL( flag2) & !hour12), !(GLOBAL( flag2) & hour12), VCC);
-- Node name is ':25' = 'count3'
-- Equation name is 'count3', location is LC2_A10, type is buried.
count3 = DFFE( _LC3_A3, GLOBAL( clk), !(GLOBAL( flag2) & !hour13), !(GLOBAL( flag2) & hour13), VCC);
-- Node name is ':24' = 'count4'
-- Equation name is 'count4', location is LC8_A8, type is buried.
count4 = DFFE( _LC2_A8, GLOBAL( clk), !(GLOBAL( flag2) & !hour20), !(GLOBAL( flag2) & hour20), VCC);
-- Node name is ':23' = 'count5'
-- Equation name is 'count5', location is LC6_A8, type is buried.
count5 = DFFE( _LC7_A8, GLOBAL( clk), !(GLOBAL( flag2) & !hour21), !(GLOBAL( flag2) & hour21), VCC);
-- Node name is ':22' = 'count6'
-- Equation name is 'count6', location is LC7_A2, type is buried.
count6 = DFFE( _LC2_A2, GLOBAL( clk), !(GLOBAL( flag2) & !hour22), !(GLOBAL( flag2) & hour22), VCC);
-- Node name is ':21' = 'count7'
-- Equation name is 'count7', location is LC3_A4, type is buried.
count7 = DFFE( _LC8_A4, GLOBAL( clk), !(GLOBAL( flag2) & !hour23), !(GLOBAL( flag2) & hour23), VCC);
-- Node name is 'time30'
-- Equation name is 'time30', type is output
time30 = count0;
-- Node name is 'time31'
-- Equation name is 'time31', type is output
time31 = count1;
-- Node name is 'time32'
-- Equation name is 'time32', type is output
time32 = count2;
-- Node name is 'time33'
-- Equation name is 'time33', type is output
time33 = count3;
-- Node name is 'time40'
-- Equation name is 'time40', type is output
time40 = count4;
-- Node name is 'time41'
-- Equation name is 'time41', type is output
time41 = count5;
-- Node name is 'time42'
-- Equation name is 'time42', type is output
time42 = count6;
-- Node name is 'time43'
-- Equation name is 'time43', type is output
time43 = count7;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A2', type is buried
!_LC4_A2 = _LC4_A2~NOT;
_LC4_A2~NOT = LCELL( _EQ001);
_EQ001 = !count1
# !count0;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ002);
_EQ002 = count2 & count3 & count4 & _LC4_A2;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A3', type is buried
_LC2_A3 = LCELL( _EQ003);
_EQ003 = count2 & !_LC4_A2
# !count2 & _LC4_A2;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:152' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = LCELL( _EQ004);
_EQ004 = !count3 & count4
# !count2 & count4
# count4 & !_LC4_A2
# count2 & count3 & !count4 & _LC4_A2;
-- Node name is '|LPM_ADD_SUB:123|addcore:adder|:153' from file "addcore.tdf" line 316, column 45
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