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📄 jishuqi_60.rpt

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-- Node name is ':8' = 'temp30' 
-- Equation name is 'temp30', location is LC5_B7, type is buried.
temp30   = DFFE( _EQ030, GLOBAL( clk), GLOBAL( en),  VCC,  VCC);
  _EQ030 = !_LC2_B9 & !temp29 &  temp30
         # !_LC2_B7 & !_LC2_B9 &  temp30
         #  _LC2_B7 & !_LC2_B9 &  temp29 & !temp30;

-- Node name is ':7' = 'temp31' 
-- Equation name is 'temp31', location is LC7_B7, type is buried.
temp31   = DFFE( _EQ031, GLOBAL( clk), GLOBAL( en),  VCC,  VCC);
  _EQ031 = !_LC2_B9 & !temp30 &  temp31
         # !_LC2_B9 & !_LC6_B7 &  temp31
         # !_LC2_B9 &  _LC6_B7 &  temp30 & !temp31;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = LCELL( _EQ032);
  _EQ032 =  temp0 &  temp1;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = LCELL( _EQ033);
  _EQ033 =  _LC4_B9 &  temp2;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:175' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = LCELL( _EQ034);
  _EQ034 =  _LC5_B15 &  temp3;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ035);
  _EQ035 =  _LC5_B15 &  temp3 &  temp4 &  temp5;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:187' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B19', type is buried 
_LC3_B19 = LCELL( _EQ036);
  _EQ036 =  _LC1_B15 &  temp6;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B19', type is buried 
_LC8_B19 = LCELL( _EQ037);
  _EQ037 =  _LC3_B19 &  temp7 &  temp8;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:199' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ038);
  _EQ038 =  _LC8_B19 &  temp9;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:207' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B12', type is buried 
_LC7_B12 = LCELL( _EQ039);
  _EQ039 =  _LC8_B19 &  temp9 &  temp10 &  temp11;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B12', type is buried 
_LC8_B12 = LCELL( _EQ040);
  _EQ040 =  _LC7_B12 &  temp12;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:219' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ041);
  _EQ041 =  _LC7_B12 &  temp12 &  temp13 &  temp14;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:223' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ042);
  _EQ042 =  _LC1_B12 &  temp15;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:231' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ043);
  _EQ043 =  _LC1_B12 &  temp15 &  temp16 &  temp17;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:235' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ044);
  _EQ044 =  _LC2_B3 &  temp18;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:243' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ045);
  _EQ045 =  _LC4_B2 &  temp19 &  temp20;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:251' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ046);
  _EQ046 =  _LC5_B2 &  temp21 &  temp22;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:259' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ047);
  _EQ047 =  _LC1_B2 &  temp23 &  temp24;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:267' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ048);
  _EQ048 =  _LC6_B1 &  temp25 &  temp26;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:275' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B7', type is buried 
_LC2_B7  = LCELL( _EQ049);
  _EQ049 =  _LC4_B1 &  temp27 &  temp28;

-- Node name is '|LPM_ADD_SUB:184|addcore:adder|:279' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = LCELL( _EQ050);
  _EQ050 =  _LC2_B7 &  temp29;

-- Node name is ':3' 
-- Equation name is '_LC6_B9', type is buried 
_LC6_B9  = DFFE( _EQ051, GLOBAL( clk), GLOBAL( en),  VCC,  VCC);
  _EQ051 = !_LC1_B1 & !_LC2_B15 &  _LC4_B9 & !_LC8_B7;

-- Node name is '~114~1' 
-- Equation name is '~114~1', location is LC1_B19, type is buried.
-- synthesized logic cell 
_LC1_B19 = LCELL( _EQ052);
  _EQ052 =  temp8
         #  temp9
         #  temp10
         #  temp11;

-- Node name is '~114~2' 
-- Equation name is '~114~2', location is LC2_B19, type is buried.
-- synthesized logic cell 
_LC2_B19 = LCELL( _EQ053);
  _EQ053 = !temp4
         # !temp5
         #  temp6
         #  temp7;

-- Node name is '~114~3' 
-- Equation name is '~114~3', location is LC2_B15, type is buried.
-- synthesized logic cell 
_LC2_B15 = LCELL( _EQ054);
  _EQ054 =  _LC1_B19
         #  _LC2_B19
         #  temp2
         # !temp3;

-- Node name is '~114~4' 
-- Equation name is '~114~4', location is LC3_B1, type is buried.
-- synthesized logic cell 
_LC3_B1  = LCELL( _EQ055);
  _EQ055 =  temp24
         #  temp25
         #  temp26
         #  temp27;

-- Node name is '~114~5' 
-- Equation name is '~114~5', location is LC3_B2, type is buried.
-- synthesized logic cell 
_LC3_B2  = LCELL( _EQ056);
  _EQ056 =  temp20
         #  temp21
         #  temp22
         #  temp23;

-- Node name is '~114~6' 
-- Equation name is '~114~6', location is LC6_B3, type is buried.
-- synthesized logic cell 
_LC6_B3  = LCELL( _EQ057);
  _EQ057 =  temp16
         #  temp17
         #  temp18
         #  temp19;

-- Node name is '~114~7' 
-- Equation name is '~114~7', location is LC3_B3, type is buried.
-- synthesized logic cell 
_LC3_B3  = LCELL( _EQ058);
  _EQ058 =  temp12
         #  temp13
         #  temp14
         #  temp15;

-- Node name is '~114~8' 
-- Equation name is '~114~8', location is LC1_B1, type is buried.
-- synthesized logic cell 
_LC1_B1  = LCELL( _EQ059);
  _EQ059 =  _LC3_B1
         #  _LC3_B2
         #  _LC6_B3
         #  _LC3_B3;

-- Node name is '~114~9' 
-- Equation name is '~114~9', location is LC8_B7, type is buried.
-- synthesized logic cell 
_LC8_B7  = LCELL( _EQ060);
  _EQ060 =  temp28
         #  temp29
         #  temp30
         #  temp31;

-- Node name is ':114' 
-- Equation name is '_LC2_B9', type is buried 
!_LC2_B9 = _LC2_B9~NOT;
_LC2_B9~NOT = LCELL( _EQ061);
  _EQ061 =  _LC2_B15
         #  _LC1_B1
         #  _LC8_B7
         # !_LC4_B9;



Project Information                                      e:\eda\jishuqi_60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,721K

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