📄 clok.rpt
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_LC4_A17 = LCELL( _EQ027);
_EQ027 = _LC3_A14 & _LC4_A21 & _LC5_A17;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:149' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ028);
_EQ028 = _LC3_A21 & !_LC8_A14
# !_LC3_A21 & _LC8_A14;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ029);
_EQ029 = !_LC3_A21 & _LC7_A14
# _LC7_A14 & !_LC8_A14
# _LC3_A21 & !_LC7_A14 & _LC8_A14;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:152' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = LCELL( _EQ030);
_EQ030 = !_LC4_A21 & _LC5_A17
# !_LC3_A14 & _LC5_A17
# _LC3_A14 & _LC4_A21 & !_LC5_A17;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:153' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ031);
_EQ031 = _LC1_A17 & !_LC4_A17
# !_LC1_A17 & _LC4_A17;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:154' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = LCELL( _EQ032);
_EQ032 = !_LC1_A17 & _LC8_A15
# !_LC4_A17 & _LC8_A15
# _LC1_A17 & _LC4_A17 & !_LC8_A15;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = LCELL( _EQ033);
_EQ033 = _LC1_A13 & !_LC1_A17
# _LC1_A13 & !_LC4_A17
# _LC1_A13 & !_LC8_A15
# !_LC1_A13 & _LC1_A17 & _LC4_A17 & _LC8_A15;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:208|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ034);
_EQ034 = !_LC1_A14 & _LC2_A14
# !_LC1_A14 & _LC5_A14;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = LCELL( _EQ035);
_EQ035 = _LC2_A17 & _LC5_A21 & _LC6_A17;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ036);
_EQ036 = _LC1_A17 & _LC3_A17 & !_LC4_A17
# !_LC1_A17 & _LC3_A17 & _LC4_A17;
-- Node name is '|COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ037);
_EQ037 = _LC1_A17 & _LC4_A15 & _LC4_A17 & !_LC8_A15
# !_LC1_A17 & _LC4_A15 & _LC8_A15
# _LC4_A15 & !_LC4_A17 & _LC8_A15;
-- Node name is '|COUNT60:14|:19'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = DFFE( _LC1_A14, GLOBAL( clk_min), VCC, VCC, !_LC1_B5);
-- Node name is '|COUNT60:14|~110~1'
-- Equation name is '_LC4_A14', type is buried
-- synthesized logic cell
_LC4_A14 = LCELL( _EQ038);
_EQ038 = !_LC8_A15
# _LC1_A13
# _LC1_A17;
-- Node name is '|COUNT60:14|~110~2'
-- Equation name is '_LC6_A14', type is buried
-- synthesized logic cell
_LC6_A14 = LCELL( _EQ039);
_EQ039 = !_LC4_A21
# _LC7_A14
# _LC3_A21;
-- Node name is '|COUNT60:14|:110'
-- Equation name is '_LC1_A14', type is buried
!_LC1_A14 = _LC1_A14~NOT;
_LC1_A14~NOT = LCELL( _EQ040);
_EQ040 = !_LC5_A17
# !_LC8_A14
# _LC4_A14
# _LC6_A14;
-- Node name is '|COUNT60:14|:173'
-- Equation name is '_LC2_A17', type is buried
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ041);
_EQ041 = _LC1_A14
# _LC3_A14 & _LC4_A21
# !_LC3_A14 & !_LC4_A21;
-- Node name is '|COUNT60:14|:199'
-- Equation name is '_LC8_A21', type is buried
!_LC8_A21 = _LC8_A21~NOT;
_LC8_A21~NOT = LCELL( _EQ042);
_EQ042 = !_LC2_A17
# !_LC2_A14 & !_LC5_A14;
-- Node name is '|COUNT60:14|:218'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ043);
_EQ043 = _LC6_A15 & !_LC7_A15 & _LC8_A21
# !_LC6_A15 & _LC7_A15 & _LC8_A21
# !_LC1_A14 & _LC7_A15 & !_LC8_A21;
-- Node name is '|COUNT60:14|:224'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = LCELL( _EQ044);
_EQ044 = !_LC3_A15 & _LC4_A15 & _LC8_A21
# _LC3_A15 & !_LC4_A15 & _LC8_A21
# !_LC1_A14 & _LC3_A15 & !_LC8_A21;
-- Node name is '|COUNT60:14|:230'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = LCELL( _EQ045);
_EQ045 = !_LC1_A15 & _LC3_A17 & _LC8_A21
# _LC1_A15 & !_LC3_A17 & _LC8_A21
# !_LC1_A14 & _LC1_A15 & !_LC8_A21;
-- Node name is '|COUNT60:14|:236'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ046);
_EQ046 = _LC5_A21 & !_LC6_A17 & _LC8_A21
# !_LC5_A21 & _LC6_A17 & _LC8_A21
# !_LC1_A14 & _LC6_A17 & !_LC8_A21;
-- Node name is '|COUNT60:14|:248'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ047);
_EQ047 = _LC2_A14 & _LC5_A14 & _LC8_A21
# !_LC2_A14 & !_LC5_A14 & _LC8_A21
# _LC2_A21;
-- Node name is '|COUNT60:14|:250'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ048);
_EQ048 = !_LC1_A14 & !_LC2_A17 & _LC5_A14;
-- Node name is '|COUNT60:14|:254'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ049);
_EQ049 = !_LC1_A14 & _LC2_A14 & !_LC2_A17
# !_LC2_A14 & _LC8_A21;
-- Node name is '|COUNT60:14|~303~1'
-- Equation name is '_LC7_A21', type is buried
-- synthesized logic cell
_LC7_A21 = LCELL( _EQ050);
_EQ050 = _LC2_A14 & _LC2_A17 & !_LC5_A21
# _LC2_A17 & _LC5_A14 & !_LC5_A21
# !_LC2_A14 & _LC2_A17 & !_LC5_A14;
Project Information e:\eda\clok.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,186K
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