📄 clok.rpt
字号:
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\clok.rpt
clok
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 13 OUTPUT 0 1 0 0 time10
72 - - A -- OUTPUT 0 1 0 0 time11
47 - - - 14 OUTPUT 0 1 0 0 time12
71 - - A -- OUTPUT 0 1 0 0 time13
70 - - A -- OUTPUT 0 1 0 0 time20
16 - - A -- OUTPUT 0 1 0 0 time21
69 - - A -- OUTPUT 0 1 0 0 time22
73 - - A -- OUTPUT 0 1 0 0 time23
21 - - B -- OUTPUT 0 1 0 0 time30
24 - - B -- OUTPUT 0 1 0 0 time31
67 - - B -- OUTPUT 0 1 0 0 time32
65 - - B -- OUTPUT 0 1 0 0 time33
22 - - B -- OUTPUT 0 1 0 0 time40
23 - - B -- OUTPUT 0 1 0 0 time41
8 - - - 03 OUTPUT 0 1 0 0 time42
25 - - B -- OUTPUT 0 1 0 0 time43
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\clok.rpt
clok
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 07 OR2 ! 0 2 0 5 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:121
- 8 - B 08 AND2 0 4 0 5 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:133
- 4 - B 03 OR2 0 2 0 5 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:150
- 6 - B 08 OR2 0 4 0 2 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:152
- 3 - B 04 OR2 0 2 0 1 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:153
- 5 - B 04 OR2 0 3 0 1 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:154
- 2 - B 04 OR2 0 4 0 1 |COUNT24:13|LPM_ADD_SUB:123|addcore:adder|:155
- 8 - B 03 OR2 0 4 0 3 |COUNT24:13|LPM_ADD_SUB:194|addcore:adder|pcarry2
- 5 - B 08 AND2 0 3 0 2 |COUNT24:13|LPM_ADD_SUB:194|addcore:adder|:133
- 6 - B 04 OR2 0 3 0 2 |COUNT24:13|LPM_ADD_SUB:194|addcore:adder|:137
- 1 - B 04 OR2 0 4 0 1 |COUNT24:13|LPM_ADD_SUB:194|addcore:adder|:141
- 8 - B 07 DFFE 1 2 1 2 |COUNT24:13|count7 (|COUNT24:13|:21)
- 8 - B 04 DFFE 1 2 1 4 |COUNT24:13|count6 (|COUNT24:13|:22)
- 4 - B 08 DFFE 1 2 1 6 |COUNT24:13|count5 (|COUNT24:13|:23)
- 2 - B 07 DFFE 1 2 1 3 |COUNT24:13|count4 (|COUNT24:13|:24)
- 5 - B 05 DFFE 1 2 1 4 |COUNT24:13|count3 (|COUNT24:13|:25)
- 1 - B 03 DFFE 1 2 1 5 |COUNT24:13|count2 (|COUNT24:13|:26)
- 6 - B 07 DFFE 1 2 1 7 |COUNT24:13|count1 (|COUNT24:13|:27)
- 1 - B 07 DFFE 1 1 1 7 |COUNT24:13|count0 (|COUNT24:13|:28)
- 4 - B 04 OR2 s 0 4 0 1 |COUNT24:13|~106~1
- 3 - B 08 OR2 ! 0 4 0 8 |COUNT24:13|:106
- 1 - B 08 OR2 ! 0 4 0 5 |COUNT24:13|:159
- 7 - B 03 OR2 0 3 0 1 |COUNT24:13|:181
- 3 - B 03 OR2 ! 0 4 0 6 |COUNT24:13|:185
- 3 - B 07 OR2 0 4 0 1 |COUNT24:13|:204
- 7 - B 04 OR2 0 4 0 1 |COUNT24:13|:210
- 7 - B 08 OR2 0 4 0 1 |COUNT24:13|:216
- 2 - B 08 OR2 0 4 0 1 |COUNT24:13|:222
- 6 - B 03 OR2 0 4 0 1 |COUNT24:13|:234
- 5 - B 03 OR2 0 4 0 1 |COUNT24:13|:235
- 7 - B 07 OR2 0 4 0 1 |COUNT24:13|:240
- 5 - B 07 OR2 0 4 0 1 |COUNT24:13|:242
- 2 - B 03 OR2 s 0 3 0 1 |COUNT24:13|~282~1
- 3 - A 14 AND2 0 3 0 3 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:125
- 4 - A 17 AND2 0 3 0 5 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:133
- 2 - A 14 OR2 0 2 0 5 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:149
- 5 - A 14 OR2 0 3 0 5 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:150
- 6 - A 17 OR2 0 3 0 2 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:152
- 1 - A 15 OR2 0 2 0 1 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:153
- 3 - A 15 OR2 0 3 0 1 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:154
- 7 - A 15 OR2 0 4 0 1 |COUNT60:14|LPM_ADD_SUB:129|addcore:adder|:155
- 5 - A 21 OR2 0 3 0 3 |COUNT60:14|LPM_ADD_SUB:208|addcore:adder|pcarry2
- 3 - A 17 AND2 0 3 0 2 |COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:133
- 4 - A 15 OR2 0 3 0 2 |COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:137
- 6 - A 15 OR2 0 4 0 1 |COUNT60:14|LPM_ADD_SUB:208|addcore:adder|:141
- 7 - B 05 DFFE + 0 2 0 8 |COUNT60:14|:19
- 1 - A 13 DFFE + 1 1 1 2 |COUNT60:14|count7 (|COUNT60:14|:23)
- 8 - A 15 DFFE + 1 1 1 4 |COUNT60:14|count6 (|COUNT60:14|:24)
- 1 - A 17 DFFE + 1 1 1 6 |COUNT60:14|count5 (|COUNT60:14|:25)
- 5 - A 17 DFFE + 1 1 1 3 |COUNT60:14|count4 (|COUNT60:14|:26)
- 4 - A 21 DFFE + 1 1 1 4 |COUNT60:14|count3 (|COUNT60:14|:27)
- 7 - A 14 DFFE + 1 1 1 3 |COUNT60:14|count2 (|COUNT60:14|:28)
- 3 - A 21 DFFE + 1 1 1 4 |COUNT60:14|count1 (|COUNT60:14|:29)
- 8 - A 14 DFFE + 1 0 1 4 |COUNT60:14|count0 (|COUNT60:14|:30)
- 4 - A 14 OR2 s 0 3 0 1 |COUNT60:14|~110~1
- 6 - A 14 OR2 s 0 3 0 1 |COUNT60:14|~110~2
- 1 - A 14 OR2 ! 0 4 0 9 |COUNT60:14|:110
- 2 - A 17 OR2 ! 0 3 0 5 |COUNT60:14|:173
- 8 - A 21 OR2 ! 0 3 0 6 |COUNT60:14|:199
- 2 - A 15 OR2 0 4 0 1 |COUNT60:14|:218
- 5 - A 15 OR2 0 4 0 1 |COUNT60:14|:224
- 8 - A 17 OR2 0 4 0 1 |COUNT60:14|:230
- 7 - A 17 OR2 0 4 0 1 |COUNT60:14|:236
- 6 - A 21 OR2 0 4 0 1 |COUNT60:14|:248
- 2 - A 21 AND2 0 3 0 1 |COUNT60:14|:250
- 1 - A 21 OR2 0 4 0 1 |COUNT60:14|:254
- 7 - A 21 OR2 s 0 4 0 1 |COUNT60:14|~303~1
- 1 - B 05 SOFT s ! 1 0 0 1 flag2~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\clok.rpt
clok
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 19/ 48( 39%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 7/ 96( 7%) 26/ 48( 54%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\clok.rpt
clok
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk_min
DFF 8 |COUNT60:14|:19
Device-Specific Information: e:\eda\clok.rpt
clok
** EQUATIONS **
clk_min : INPUT;
flag2 : INPUT;
hour10 : INPUT;
hour11 : INPUT;
hour12 : INPUT;
hour13 : INPUT;
hour20 : INPUT;
hour21 : INPUT;
hour22 : INPUT;
hour23 : INPUT;
sec10 : INPUT;
sec11 : INPUT;
sec12 : INPUT;
sec13 : INPUT;
sec20 : INPUT;
sec21 : INPUT;
sec22 : INPUT;
sec23 : INPUT;
-- Node name is 'flag2~1'
-- Equation name is 'flag2~1', location is LC1_B5, type is buried.
-- synthesized logic cell
!_LC1_B5 = _LC1_B5~NOT;
_LC1_B5~NOT = LCELL(!flag2);
-- Node name is 'time10'
-- Equation name is 'time10', type is output
time10 = _LC8_A14;
-- Node name is 'time11'
-- Equation name is 'time11', type is output
time11 = _LC3_A21;
-- Node name is 'time12'
-- Equation name is 'time12', type is output
time12 = _LC7_A14;
-- Node name is 'time13'
-- Equation name is 'time13', type is output
time13 = _LC4_A21;
-- Node name is 'time20'
-- Equation name is 'time20', type is output
time20 = _LC5_A17;
-- Node name is 'time21'
-- Equation name is 'time21', type is output
time21 = _LC1_A17;
-- Node name is 'time22'
-- Equation name is 'time22', type is output
time22 = _LC8_A15;
-- Node name is 'time23'
-- Equation name is 'time23', type is output
time23 = _LC1_A13;
-- Node name is 'time30'
-- Equation name is 'time30', type is output
time30 = _LC1_B7;
-- Node name is 'time31'
-- Equation name is 'time31', type is output
time31 = _LC6_B7;
-- Node name is 'time32'
-- Equation name is 'time32', type is output
time32 = _LC1_B3;
-- Node name is 'time33'
-- Equation name is 'time33', type is output
time33 = _LC5_B5;
-- Node name is 'time40'
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