📄 count60.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - - 22 OUTPUT 0 1 0 0 co
66 - - B -- OUTPUT 0 1 0 0 time10
64 - - B -- OUTPUT 0 1 0 0 time11
78 - - - 24 OUTPUT 0 1 0 0 time12
23 - - B -- OUTPUT 0 1 0 0 time13
21 - - B -- OUTPUT 0 1 0 0 time20
22 - - B -- OUTPUT 0 1 0 0 time21
67 - - B -- OUTPUT 0 1 0 0 time22
65 - - B -- OUTPUT 0 1 0 0 time23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\count60.rpt
count60
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 21 SOFT s ! 1 0 0 1 flag2~1
- 3 - B 24 AND2 0 3 0 3 |LPM_ADD_SUB:129|addcore:adder|:125
- 8 - B 13 AND2 0 3 0 5 |LPM_ADD_SUB:129|addcore:adder|:133
- 2 - B 16 OR2 0 2 0 5 |LPM_ADD_SUB:129|addcore:adder|:149
- 1 - B 24 OR2 0 3 0 5 |LPM_ADD_SUB:129|addcore:adder|:150
- 5 - B 13 OR2 0 3 0 2 |LPM_ADD_SUB:129|addcore:adder|:152
- 2 - B 17 OR2 0 2 0 1 |LPM_ADD_SUB:129|addcore:adder|:153
- 3 - B 17 OR2 0 3 0 1 |LPM_ADD_SUB:129|addcore:adder|:154
- 7 - B 17 OR2 0 4 0 1 |LPM_ADD_SUB:129|addcore:adder|:155
- 8 - B 16 OR2 0 3 0 3 |LPM_ADD_SUB:208|addcore:adder|pcarry2
- 4 - B 13 AND2 0 3 0 2 |LPM_ADD_SUB:208|addcore:adder|:133
- 4 - B 17 OR2 0 3 0 2 |LPM_ADD_SUB:208|addcore:adder|:137
- 6 - B 17 OR2 0 4 0 1 |LPM_ADD_SUB:208|addcore:adder|:141
- 4 - B 21 DFFE + 0 2 1 0 :19
- 8 - B 20 DFFE + 1 1 1 2 count7 (:23)
- 1 - B 17 DFFE + 1 1 1 4 count6 (:24)
- 2 - B 13 DFFE + 1 1 1 6 count5 (:25)
- 1 - B 13 DFFE + 1 1 1 3 count4 (:26)
- 4 - B 16 DFFE + 1 1 1 4 count3 (:27)
- 5 - B 24 DFFE + 1 1 1 3 count2 (:28)
- 7 - B 24 DFFE + 1 1 1 4 count1 (:29)
- 2 - B 24 DFFE + 1 0 1 4 count0 (:30)
- 4 - B 24 OR2 s 0 3 0 1 ~110~1
- 8 - B 24 OR2 s 0 3 0 1 ~110~2
- 6 - B 24 OR2 ! 0 4 0 9 :110
- 3 - B 13 OR2 ! 0 3 0 5 :173
- 1 - B 16 OR2 ! 0 3 0 6 :199
- 8 - B 17 OR2 0 4 0 1 :218
- 5 - B 17 OR2 0 4 0 1 :224
- 7 - B 13 OR2 0 4 0 1 :230
- 6 - B 13 OR2 0 4 0 1 :236
- 3 - B 16 OR2 0 4 0 1 :248
- 6 - B 16 AND2 0 3 0 1 :250
- 5 - B 16 OR2 0 4 0 1 :254
- 7 - B 16 OR2 s 0 4 0 1 ~303~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\count60.rpt
count60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 22/ 48( 45%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\count60.rpt
count60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: e:\eda\count60.rpt
count60
** EQUATIONS **
clk : INPUT;
flag2 : INPUT;
sec10 : INPUT;
sec11 : INPUT;
sec12 : INPUT;
sec13 : INPUT;
sec20 : INPUT;
sec21 : INPUT;
sec22 : INPUT;
sec23 : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC4_B21;
-- Node name is ':30' = 'count0'
-- Equation name is 'count0', location is LC2_B24, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), !(GLOBAL( flag2) & !sec10), !(GLOBAL( flag2) & sec10), VCC);
-- Node name is ':29' = 'count1'
-- Equation name is 'count1', location is LC7_B24, type is buried.
count1 = DFFE( _LC5_B16, GLOBAL( clk), !(GLOBAL( flag2) & !sec11), !(GLOBAL( flag2) & sec11), VCC);
-- Node name is ':28' = 'count2'
-- Equation name is 'count2', location is LC5_B24, type is buried.
count2 = DFFE( _LC3_B16, GLOBAL( clk), !(GLOBAL( flag2) & !sec12), !(GLOBAL( flag2) & sec12), VCC);
-- Node name is ':27' = 'count3'
-- Equation name is 'count3', location is LC4_B16, type is buried.
count3 = DFFE( _LC7_B16, GLOBAL( clk), !(GLOBAL( flag2) & !sec13), !(GLOBAL( flag2) & sec13), VCC);
-- Node name is ':26' = 'count4'
-- Equation name is 'count4', location is LC1_B13, type is buried.
count4 = DFFE( _LC6_B13, GLOBAL( clk), !(GLOBAL( flag2) & !sec20), !(GLOBAL( flag2) & sec20), VCC);
-- Node name is ':25' = 'count5'
-- Equation name is 'count5', location is LC2_B13, type is buried.
count5 = DFFE( _LC7_B13, GLOBAL( clk), !(GLOBAL( flag2) & !sec21), !(GLOBAL( flag2) & sec21), VCC);
-- Node name is ':24' = 'count6'
-- Equation name is 'count6', location is LC1_B17, type is buried.
count6 = DFFE( _LC5_B17, GLOBAL( clk), !(GLOBAL( flag2) & !sec22), !(GLOBAL( flag2) & sec22), VCC);
-- Node name is ':23' = 'count7'
-- Equation name is 'count7', location is LC8_B20, type is buried.
count7 = DFFE( _LC8_B17, GLOBAL( clk), !(GLOBAL( flag2) & !sec23), !(GLOBAL( flag2) & sec23), VCC);
-- Node name is 'flag2~1'
-- Equation name is 'flag2~1', location is LC1_B21, type is buried.
-- synthesized logic cell
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL(!flag2);
-- Node name is 'time10'
-- Equation name is 'time10', type is output
time10 = count0;
-- Node name is 'time11'
-- Equation name is 'time11', type is output
time11 = count1;
-- Node name is 'time12'
-- Equation name is 'time12', type is output
time12 = count2;
-- Node name is 'time13'
-- Equation name is 'time13', type is output
time13 = count3;
-- Node name is 'time20'
-- Equation name is 'time20', type is output
time20 = count4;
-- Node name is 'time21'
-- Equation name is 'time21', type is output
time21 = count5;
-- Node name is 'time22'
-- Equation name is 'time22', type is output
time22 = count6;
-- Node name is 'time23'
-- Equation name is 'time23', type is output
time23 = count7;
-- Node name is '|LPM_ADD_SUB:129|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ001);
_EQ001 = count0 & count1 & count2;
-- Node name is '|LPM_ADD_SUB:129|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ002);
_EQ002 = count3 & count4 & _LC3_B24;
-- Node name is '|LPM_ADD_SUB:129|addcore:adder|:149' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ003);
_EQ003 = !count0 & count1
# count0 & !count1;
-- Node name is '|LPM_ADD_SUB:129|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ004);
_EQ004 = !count1 & count2
# !count0 & count2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -