📄 jijia.rpt
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-- synthesized logic cell
!_LC7_A24 = _LC7_A24~NOT;
_LC7_A24~NOT = LCELL( _EQ049);
_EQ049 = !km20 & !km21 & !km22 & !km23;
-- Node name is '~629~2'
-- Equation name is '~629~2', location is LC8_A24, type is buried.
-- synthesized logic cell
!_LC8_A24 = _LC8_A24~NOT;
_LC8_A24~NOT = LCELL( _EQ050);
_EQ050 = !km11 & !km12
# !km10 & !km12;
-- Node name is ':629'
-- Equation name is '_LC1_A24', type is buried
!_LC1_A24 = _LC1_A24~NOT;
_LC1_A24~NOT = LCELL( _EQ051);
_EQ051 = !km13 & !_LC7_A24 & !_LC8_A24 & !wait_en;
-- Node name is ':676'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ052);
_EQ052 = _LC4_A6 & _LC8_A1 & mm11
# _LC1_A24 & !_LC4_A6 & _LC8_A1 & !mm11
# !_LC4_A6 & !_LC8_A1 & mm11
# _LC1_A24 & _LC4_A6 & !_LC8_A1 & !mm11
# !_LC1_A24 & mm11;
-- Node name is ':682'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ053);
_EQ053 = _LC6_A1 & _LC7_A1 & mm10
# _LC1_A24 & !_LC6_A1 & _LC7_A1 & !mm10
# !_LC6_A1 & !_LC7_A1 & mm10
# _LC1_A24 & _LC6_A1 & !_LC7_A1 & !mm10
# !_LC1_A24 & mm10;
-- Node name is ':688'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ054);
_EQ054 = _LC3_A10 & _LC4_A1 & mm9
# _LC1_A24 & _LC3_A10 & !_LC4_A1 & !mm9
# !_LC3_A10 & !_LC4_A1 & mm9
# _LC1_A24 & !_LC3_A10 & _LC4_A1 & !mm9
# !_LC1_A24 & mm9;
-- Node name is ':694'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ055);
_EQ055 = _LC6_A10 & _LC8_A10 & mm8
# _LC1_A24 & !_LC6_A10 & _LC8_A10 & !mm8
# !_LC6_A10 & !_LC8_A10 & mm8
# _LC1_A24 & _LC6_A10 & !_LC8_A10 & !mm8
# !_LC1_A24 & mm8;
-- Node name is ':700'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ056);
_EQ056 = !_LC2_A5 & !_LC7_A10 & mm7
# _LC1_A24 & !_LC2_A5 & _LC7_A10 & !mm7
# _LC2_A5 & _LC7_A10 & mm7
# _LC1_A24 & _LC2_A5 & !_LC7_A10 & !mm7
# !_LC1_A24 & mm7;
-- Node name is ':706'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = LCELL( _EQ057);
_EQ057 = !_LC7_A5 & !_LC8_A5 & mm6
# _LC1_A24 & !_LC7_A5 & _LC8_A5 & !mm6
# _LC7_A5 & _LC8_A5 & mm6
# _LC1_A24 & _LC7_A5 & !_LC8_A5 & !mm6
# !_LC1_A24 & mm6;
-- Node name is ':712'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ058);
_EQ058 = !_LC2_A24 & !_LC6_A5 & mm5
# _LC1_A24 & !_LC2_A24 & _LC6_A5 & !mm5
# _LC2_A24 & _LC6_A5 & mm5
# _LC1_A24 & _LC2_A24 & !_LC6_A5 & !mm5
# !_LC1_A24 & mm5;
-- Node name is ':718'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ059);
_EQ059 = !_LC5_A24 & !_LC8_A19 & mm4
# _LC1_A24 & _LC5_A24 & !_LC8_A19 & !mm4
# _LC5_A24 & _LC8_A19 & mm4
# _LC1_A24 & !_LC5_A24 & _LC8_A19 & !mm4
# !_LC1_A24 & mm4;
-- Node name is ':724'
-- Equation name is '_LC6_A19', type is buried
!_LC6_A19 = _LC6_A19~NOT;
_LC6_A19~NOT = LCELL( _EQ060);
_EQ060 = _LC2_A19 & _LC3_A19 & !mm3
# !_LC2_A19 & !_LC3_A19 & !mm3
# !_LC1_A24 & !mm3
# _LC1_A24 & _LC2_A19 & !_LC3_A19 & mm3
# _LC1_A24 & !_LC2_A19 & _LC3_A19 & mm3;
-- Node name is ':730'
-- Equation name is '_LC7_A19', type is buried
!_LC7_A19 = _LC7_A19~NOT;
_LC7_A19~NOT = LCELL( _EQ061);
_EQ061 = _LC2_A17 & _LC6_A17 & !mm2
# !_LC2_A17 & !_LC6_A17 & !mm2
# !_LC1_A24 & !mm2
# _LC1_A24 & !_LC2_A17 & _LC6_A17 & mm2
# _LC1_A24 & _LC2_A17 & !_LC6_A17 & mm2;
-- Node name is ':736'
-- Equation name is '_LC8_A17', type is buried
!_LC8_A17 = _LC8_A17~NOT;
_LC8_A17~NOT = LCELL( _EQ062);
_EQ062 = !_LC7_A17 & !mm1
# !_LC1_A24 & !mm1
# _LC1_A24 & _LC7_A17 & mm1;
-- Node name is ':748'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ063);
_EQ063 = !_LC7_A19 & !_LC8_A17;
-- Node name is ':752'
-- Equation name is '_LC6_A24', type is buried
!_LC6_A24 = _LC6_A24~NOT;
_LC6_A24~NOT = LCELL( _EQ064);
_EQ064 = !_LC6_A19
# _LC1_A19;
-- Node name is ':775'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ065);
_EQ065 = _LC1_A1 & !_LC6_A6 & _LC6_A24 & _LC8_A7
# _LC6_A6 & !_LC8_A7
# !_LC1_A1 & _LC6_A6
# _LC6_A6 & !_LC6_A24;
-- Node name is ':781'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ066);
_EQ066 = !_LC1_A1 & _LC6_A24 & _LC8_A7
# _LC1_A1 & !_LC8_A7
# _LC1_A1 & !_LC6_A24;
-- Node name is ':787'
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = LCELL( _EQ067);
_EQ067 = !_LC2_A1 & _LC6_A24 & _LC7_A7
# _LC2_A1 & !_LC7_A7
# _LC2_A1 & !_LC6_A24;
-- Node name is ':793'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = LCELL( _EQ068);
_EQ068 = !_LC1_A10 & _LC3_A7 & _LC4_A10 & _LC6_A24
# _LC1_A10 & !_LC3_A7
# _LC1_A10 & !_LC4_A10
# _LC1_A10 & !_LC6_A24;
-- Node name is ':799'
-- Equation name is '_LC6_A7', type is buried
!_LC6_A7 = _LC6_A7~NOT;
_LC6_A7~NOT = LCELL( _EQ069);
_EQ069 = !_LC3_A7 & !_LC4_A10
# !_LC4_A10 & !_LC6_A24
# _LC3_A7 & _LC4_A10 & _LC6_A24;
-- Node name is ':805'
-- Equation name is '_LC1_A7', type is buried
!_LC1_A7 = _LC1_A7~NOT;
_LC1_A7~NOT = LCELL( _EQ070);
_EQ070 = !_LC3_A24 & !_LC5_A5
# !_LC3_A5 & !_LC5_A5
# _LC3_A5 & _LC3_A24 & _LC5_A5 & _LC6_A24
# !_LC5_A5 & !_LC6_A24;
-- Node name is ':811'
-- Equation name is '_LC2_A7', type is buried
!_LC2_A7 = _LC2_A7~NOT;
_LC2_A7~NOT = LCELL( _EQ071);
_EQ071 = !_LC3_A5 & !_LC3_A24
# _LC3_A5 & _LC3_A24 & _LC6_A24
# !_LC3_A5 & !_LC6_A24;
-- Node name is ':847'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ072);
_EQ072 = !_LC1_A7 & !_LC2_A7;
-- Node name is ':851'
-- Equation name is '_LC8_A9', type is buried
!_LC8_A9 = _LC8_A9~NOT;
_LC8_A9~NOT = LCELL( _EQ073);
_EQ073 = !_LC6_A7
# _LC2_A9;
Project Information e:\eda\jijia.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,995K
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