📄 jijia.rpt
字号:
19 - - A -- OUTPUT 0 1 0 0 count30
69 - - A -- OUTPUT 0 1 0 0 count31
17 - - A -- OUTPUT 0 1 0 0 count32
5 - - - 05 OUTPUT 0 1 0 0 count33
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\jijia.rpt
jijia
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 05 OR2 2 0 0 3 |LPM_ADD_SUB:290|addcore:adder|pcarry5
- 4 - A 05 OR2 1 1 0 2 |LPM_ADD_SUB:290|addcore:adder|pcarry6
- 2 - A 10 OR2 3 1 0 3 |LPM_ADD_SUB:290|addcore:adder|pcarry8
- 3 - A 01 OR2 2 1 0 1 |LPM_ADD_SUB:290|addcore:adder|pcarry10
- 6 - A 17 OR2 0 4 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry1
- 2 - A 19 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry2
- 8 - A 19 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry3
- 2 - A 24 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry4
- 7 - A 05 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry5
- 2 - A 05 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry6
- 8 - A 10 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry7
- 3 - A 10 OR2 1 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry8
- 7 - A 01 OR2 0 3 0 2 |LPM_ADD_SUB:666|addcore:adder|pcarry9
- 8 - A 01 OR2 1 3 0 1 |LPM_ADD_SUB:666|addcore:adder|pcarry10
- 7 - A 17 OR2 s 2 2 0 1 |LPM_ADD_SUB:666|addcore:adder|~142~1
- 3 - A 07 AND2 0 4 0 4 |LPM_ADD_SUB:765|addcore:adder|:107
- 7 - A 07 AND2 0 3 0 1 |LPM_ADD_SUB:765|addcore:adder|:115
- 8 - A 07 AND2 0 4 0 2 |LPM_ADD_SUB:765|addcore:adder|:119
- 3 - A 06 AND2 0 3 0 2 |LPM_ADD_SUB:864|addcore:adder|:119
- 2 - B 08 AND2 ! 2 0 0 1 :179
- 3 - B 08 OR2 s 3 1 0 1 ~188~1
- 1 - B 08 OR2 ! 3 1 0 8 :188
- 4 - A 06 OR2 2 2 0 1 :420
- 5 - A 01 OR2 2 2 0 2 :424
- 6 - A 01 AND2 1 1 0 1 :429
- 4 - A 01 OR2 2 2 0 2 :438
- 5 - A 10 OR2 2 2 0 2 :442
- 6 - A 10 AND2 1 1 0 1 :447
- 7 - A 10 OR2 2 2 0 2 :456
- 8 - A 05 OR2 2 2 0 2 :465
- 6 - A 05 OR2 3 1 0 2 :474
- 5 - A 24 OR2 2 1 0 2 :483
- 3 - A 19 AND2 2 0 0 2 :492
- 2 - A 17 AND2 2 0 0 2 :501
- 5 - A 17 AND2 2 0 0 1 :510
- 4 - A 17 OR2 2 0 0 2 :517
- 5 - A 06 DFFE + 0 4 1 1 mm11 (:546)
- 2 - A 06 DFFE + 0 3 1 2 mm10 (:547)
- 8 - A 06 DFFE + 0 3 1 2 mm9 (:548)
- 7 - A 09 DFFE + 0 3 1 2 mm8 (:549)
- 3 - A 09 DFFE + 0 3 1 2 mm7 (:550)
- 1 - A 09 DFFE + ! 0 4 1 2 mm6 (:551)
- 5 - A 09 DFFE + 0 3 1 2 mm5 (:552)
- 4 - A 24 DFFE + ! 0 3 1 2 mm4 (:553)
- 4 - A 19 DFFE + 0 3 1 2 mm3 (:554)
- 5 - A 19 DFFE + 0 4 1 2 mm2 (:555)
- 3 - A 17 DFFE + 0 3 1 2 mm1 (:556)
- 1 - A 17 DFFE + 2 1 1 2 mm0 (:557)
- 7 - A 24 AND2 s ! 4 0 0 1 ~629~1
- 8 - A 24 OR2 s ! 3 0 0 1 ~629~2
- 1 - A 24 AND2 ! 2 2 0 12 :629
- 6 - A 06 OR2 0 4 0 1 :676
- 1 - A 01 OR2 0 4 0 2 :682
- 2 - A 01 OR2 0 4 0 2 :688
- 1 - A 10 OR2 0 4 0 3 :694
- 4 - A 10 OR2 0 4 0 4 :700
- 5 - A 05 OR2 0 4 0 2 :706
- 3 - A 05 OR2 0 4 0 3 :712
- 3 - A 24 OR2 0 4 0 4 :718
- 6 - A 19 OR2 ! 0 4 0 5 :724
- 7 - A 19 OR2 ! 0 4 0 3 :730
- 8 - A 17 OR2 ! 0 3 0 4 :736
- 1 - A 19 AND2 0 2 0 4 :748
- 6 - A 24 OR2 ! 0 2 0 8 :752
- 7 - A 06 OR2 0 4 0 1 :775
- 1 - A 06 OR2 0 3 0 2 :781
- 5 - A 07 OR2 0 3 0 2 :787
- 4 - A 07 OR2 0 4 0 3 :793
- 6 - A 07 OR2 ! 0 3 0 4 :799
- 1 - A 07 OR2 ! 0 4 0 3 :805
- 2 - A 07 OR2 ! 0 3 0 4 :811
- 2 - A 09 AND2 0 2 0 4 :847
- 8 - A 09 OR2 ! 0 2 0 5 :851
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\jijia.rpt
jijia
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 28/ 48( 58%) 20/ 48( 41%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 0/ 48( 0%) 8/16( 50%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\jijia.rpt
jijia
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: e:\eda\jijia.rpt
jijia
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 12 rst
Device-Specific Information: e:\eda\jijia.rpt
jijia
** EQUATIONS **
clk : INPUT;
km10 : INPUT;
km11 : INPUT;
km12 : INPUT;
km13 : INPUT;
km20 : INPUT;
km21 : INPUT;
km22 : INPUT;
km23 : INPUT;
price10 : INPUT;
price11 : INPUT;
price12 : INPUT;
price13 : INPUT;
price20 : INPUT;
price21 : INPUT;
price22 : INPUT;
price23 : INPUT;
price30 : INPUT;
price31 : INPUT;
price32 : INPUT;
price33 : INPUT;
rst : INPUT;
time30 : INPUT;
time31 : INPUT;
time32 : INPUT;
time33 : INPUT;
time40 : INPUT;
time41 : INPUT;
time42 : INPUT;
time43 : INPUT;
wait_en : INPUT;
-- Node name is 'count10'
-- Equation name is 'count10', type is output
count10 = mm0;
-- Node name is 'count11'
-- Equation name is 'count11', type is output
count11 = mm1;
-- Node name is 'count12'
-- Equation name is 'count12', type is output
count12 = mm2;
-- Node name is 'count13'
-- Equation name is 'count13', type is output
count13 = mm3;
-- Node name is 'count20'
-- Equation name is 'count20', type is output
count20 = mm4;
-- Node name is 'count21'
-- Equation name is 'count21', type is output
count21 = mm5;
-- Node name is 'count22'
-- Equation name is 'count22', type is output
count22 = mm6;
-- Node name is 'count23'
-- Equation name is 'count23', type is output
count23 = mm7;
-- Node name is 'count30'
-- Equation name is 'count30', type is output
count30 = mm8;
-- Node name is 'count31'
-- Equation name is 'count31', type is output
count31 = mm9;
-- Node name is 'count32'
-- Equation name is 'count32', type is output
count32 = mm10;
-- Node name is 'count33'
-- Equation name is 'count33', type is output
count33 = mm11;
-- Node name is ':557' = 'mm0'
-- Equation name is 'mm0', location is LC1_A17, type is buried.
mm0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ001 = mm0 & !price10 & !wait_en
# _LC1_A24 & !mm0 & price10
# _LC1_A24 & !mm0 & wait_en
# !_LC1_A24 & mm0;
-- Node name is ':556' = 'mm1'
-- Equation name is 'mm1', location is LC3_A17, type is buried.
mm1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ002 = !_LC1_A19 & _LC6_A19 & !_LC8_A17
# !_LC6_A19 & _LC8_A17;
-- Node name is ':555' = 'mm2'
-- Equation name is 'mm2', location is LC5_A19, type is buried.
mm2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ003 = !_LC6_A19 & _LC7_A19
# _LC1_A19 & _LC7_A19
# _LC7_A19 & _LC8_A17
# !_LC1_A19 & _LC6_A19 & !_LC7_A19 & !_LC8_A17;
-- Node name is ':554' = 'mm3'
-- Equation name is 'mm3', location is LC4_A19, type is buried.
mm3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ004 = _LC6_A19 & !_LC7_A19 & !_LC8_A17;
-- Node name is ':553' = 'mm4'
-- Equation name is 'mm4', location is LC4_A24, type is buried.
!mm4 = mm4~NOT;
mm4~NOT = DFFE( _EQ005, GLOBAL( clk), GLOBAL( rst), VCC, VCC);
_EQ005 = !_LC1_A19 & _LC3_A24 & _LC6_A19
# !_LC3_A24 & !_LC6_A19
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