📄 saomiaoxianshi.rpt
字号:
# flag0 & !switch;
-- Node name is '~650~1'
-- Equation name is '~650~1', location is LC3_C17, type is buried.
-- synthesized logic cell
_LC3_C17 = LCELL( _EQ013);
_EQ013 = flag2
# flag0 & switch;
-- Node name is '~650~2'
-- Equation name is '~650~2', location is LC4_C17, type is buried.
-- synthesized logic cell
_LC4_C17 = LCELL( _EQ014);
_EQ014 = count0 & !count1 & _LC1_C17
# !count0 & count1 & _LC3_C17;
-- Node name is ':702'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = LCELL( _EQ015);
_EQ015 = !count0 & !count1 & !count2;
-- Node name is ':706'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = LCELL( _EQ016);
_EQ016 = count0 & !count1 & !count2;
-- Node name is ':710'
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = LCELL( _EQ017);
_EQ017 = !count0 & count1 & !count2;
-- Node name is ':714'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = LCELL( _EQ018);
_EQ018 = count0 & count1 & !count2;
-- Node name is ':718'
-- Equation name is '_LC4_C20', type is buried
!_LC4_C20 = _LC4_C20~NOT;
_LC4_C20~NOT = LCELL( _EQ019);
_EQ019 = count1
# count0
# !count2;
-- Node name is ':722'
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = LCELL( _EQ020);
_EQ020 = count0 & !count1 & count2;
-- Node name is ':742'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = LCELL( _EQ021);
_EQ021 = _LC4_C20 & p53;
-- Node name is ':743'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = LCELL( _EQ022);
_EQ022 = !_LC4_C20 & !_LC7_C20 & p73
# !_LC4_C20 & _LC7_C20 & p63;
-- Node name is ':747'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = LCELL( _EQ023);
_EQ023 = _LC1_C16 & !_LC6_C20
# _LC2_C16 & !_LC6_C20
# _LC6_C20 & p43;
-- Node name is ':760'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = LCELL( _EQ024);
_EQ024 = _LC1_C20 & p23;
-- Node name is ':761'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = LCELL( _EQ025);
_EQ025 = !_LC1_C20 & !_LC3_C20 & _LC8_C16
# !_LC1_C20 & _LC3_C20 & p33;
-- Node name is ':765'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ026);
_EQ026 = !_LC2_C17 & _LC7_C18
# !_LC2_C17 & _LC8_C17
# _LC2_C17 & p13;
-- Node name is ':771'
-- Equation name is '_LC1_C18', type is buried
!_LC1_C18 = _LC1_C18~NOT;
_LC1_C18~NOT = LCELL( _EQ027);
_EQ027 = !p62 & !p72
# _LC7_C20 & !p62
# !_LC7_C20 & !p72;
-- Node name is ':774'
-- Equation name is '_LC2_C18', type is buried
!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL( _EQ028);
_EQ028 = !_LC1_C18 & !p52
# !_LC1_C18 & !_LC4_C20
# _LC4_C20 & !p52;
-- Node name is ':777'
-- Equation name is '_LC4_C18', type is buried
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ029);
_EQ029 = !_LC2_C18 & !p42
# _LC6_C20 & !p42
# !_LC2_C18 & !_LC6_C20;
-- Node name is ':780'
-- Equation name is '_LC5_C18', type is buried
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ030);
_EQ030 = !_LC4_C18 & !p32
# _LC3_C20 & !p32
# !_LC3_C20 & !_LC4_C18;
-- Node name is ':783'
-- Equation name is '_LC6_C18', type is buried
!_LC6_C18 = _LC6_C18~NOT;
_LC6_C18~NOT = LCELL( _EQ031);
_EQ031 = !_LC5_C18 & !p22
# _LC1_C20 & !p22
# !_LC1_C20 & !_LC5_C18;
-- Node name is ':786'
-- Equation name is '_LC8_C18', type is buried
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ032);
_EQ032 = !_LC6_C18 & !p12
# _LC2_C17 & !p12
# !_LC2_C17 & !_LC6_C18;
-- Node name is ':792'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = LCELL( _EQ033);
_EQ033 = !_LC7_C20 & p71
# _LC7_C20 & p61;
-- Node name is ':795'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = LCELL( _EQ034);
_EQ034 = _LC4_C20 & p51
# _LC3_C16 & !_LC4_C20;
-- Node name is ':798'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = LCELL( _EQ035);
_EQ035 = _LC5_C16 & !_LC6_C20
# _LC6_C20 & p41;
-- Node name is ':801'
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ036);
_EQ036 = !_LC3_C20 & _LC6_C16
# _LC3_C20 & p31;
-- Node name is ':804'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = LCELL( _EQ037);
_EQ037 = !_LC1_C20 & _LC7_C16
# _LC1_C20 & p21;
-- Node name is ':807'
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = LCELL( _EQ038);
_EQ038 = !_LC2_C17 & _LC4_C16
# _LC2_C17 & p11;
-- Node name is ':813'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = LCELL( _EQ039);
_EQ039 = !_LC7_C20 & p70
# _LC7_C20 & p60;
-- Node name is ':816'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ040);
_EQ040 = _LC4_C20 & p50
# _LC1_C14 & !_LC4_C20;
-- Node name is ':819'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ041);
_EQ041 = _LC2_C14 & !_LC6_C20
# _LC6_C20 & p40;
-- Node name is ':826'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ042);
_EQ042 = _LC1_C20 & p20;
-- Node name is ':827'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = LCELL( _EQ043);
_EQ043 = !_LC1_C20 & !_LC3_C20 & _LC6_C14
# !_LC1_C20 & _LC3_C20 & p30;
-- Node name is ':828'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ044);
_EQ044 = !_LC2_C17 & _LC3_C18
# _LC1_C22 & !_LC2_C17
# _LC2_C17 & p10;
Project Information e:\eda\saomiaoxianshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,764K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -