📄 saomiaoxianshi.rpt
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Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 15 DFFE + 0 1 1 0 :34
- 7 - C 19 DFFE + 0 1 1 0 :36
- 4 - C 24 DFFE + 0 1 1 0 :38
- 8 - C 21 DFFE + 0 4 1 0 :40
- 4 - C 21 DFFE + 0 4 1 0 :42
- 7 - C 21 DFFE + 0 4 1 0 :44
- 2 - C 21 DFFE + 0 4 1 0 :46
- 1 - C 21 DFFE + 0 4 1 0 :48
- 5 - C 21 DFFE + 0 4 1 0 :50
- 3 - C 21 DFFE + 0 4 1 0 :52
- 5 - C 17 DFFE + 0 2 1 0 :54
- 8 - C 20 DFFE + 0 2 0 10 count2 (:56)
- 2 - C 20 DFFE + 0 2 0 10 count1 (:57)
- 5 - C 20 DFFE + 0 2 0 10 count0 (:58)
- 1 - C 17 OR2 s 3 0 0 1 ~409~1
- 3 - C 17 OR2 s 3 0 0 1 ~650~1
- 4 - C 17 OR2 s 0 4 0 1 ~650~2
- 2 - C 17 AND2 0 3 0 4 :702
- 1 - C 20 AND2 0 3 0 6 :706
- 3 - C 20 AND2 0 3 0 4 :710
- 6 - C 20 AND2 0 3 0 4 :714
- 4 - C 20 OR2 ! 0 3 0 5 :718
- 7 - C 20 AND2 0 3 0 4 :722
- 1 - C 16 AND2 1 1 0 1 :742
- 2 - C 16 OR2 2 2 0 1 :743
- 8 - C 16 OR2 1 3 0 1 :747
- 8 - C 17 AND2 1 1 0 1 :760
- 7 - C 18 OR2 1 3 0 1 :761
- 7 - C 17 OR2 1 3 0 7 :765
- 1 - C 18 OR2 ! 2 1 0 1 :771
- 2 - C 18 OR2 ! 1 2 0 1 :774
- 4 - C 18 OR2 ! 1 2 0 1 :777
- 5 - C 18 OR2 ! 1 2 0 1 :780
- 6 - C 18 OR2 ! 1 2 0 1 :783
- 8 - C 18 OR2 ! 1 2 0 7 :786
- 3 - C 16 OR2 2 1 0 1 :792
- 5 - C 16 OR2 1 2 0 1 :795
- 6 - C 16 OR2 1 2 0 1 :798
- 7 - C 16 OR2 1 2 0 1 :801
- 4 - C 16 OR2 1 2 0 1 :804
- 6 - C 17 OR2 1 2 0 7 :807
- 1 - C 14 OR2 2 1 0 1 :813
- 2 - C 14 OR2 1 2 0 1 :816
- 6 - C 14 OR2 1 2 0 1 :819
- 1 - C 22 AND2 1 1 0 1 :826
- 3 - C 18 OR2 1 3 0 1 :827
- 6 - C 21 OR2 1 3 0 7 :828
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\eda\saomiaoxianshi.rpt
saomiaoxianshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 19/ 96( 19%) 0/ 48( 0%) 29/ 48( 60%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\saomiaoxianshi.rpt
saomiaoxianshi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
Device-Specific Information: e:\eda\saomiaoxianshi.rpt
saomiaoxianshi
** EQUATIONS **
clk : INPUT;
flag0 : INPUT;
flag1 : INPUT;
flag2 : INPUT;
p10 : INPUT;
p11 : INPUT;
p12 : INPUT;
p13 : INPUT;
p20 : INPUT;
p21 : INPUT;
p22 : INPUT;
p23 : INPUT;
p30 : INPUT;
p31 : INPUT;
p32 : INPUT;
p33 : INPUT;
p40 : INPUT;
p41 : INPUT;
p42 : INPUT;
p43 : INPUT;
p50 : INPUT;
p51 : INPUT;
p52 : INPUT;
p53 : INPUT;
p60 : INPUT;
p61 : INPUT;
p62 : INPUT;
p63 : INPUT;
p70 : INPUT;
p71 : INPUT;
p72 : INPUT;
p73 : INPUT;
switch : INPUT;
-- Node name is 'choice0'
-- Equation name is 'choice0', type is output
choice0 = _LC4_C24;
-- Node name is 'choice1'
-- Equation name is 'choice1', type is output
choice1 = _LC7_C19;
-- Node name is 'choice2'
-- Equation name is 'choice2', type is output
choice2 = _LC5_C15;
-- Node name is ':58' = 'count0'
-- Equation name is 'count0', location is LC5_C20, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count0 & !count2
# !count0 & !count1;
-- Node name is ':57' = 'count1'
-- Equation name is 'count1', location is LC2_C20, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count0 & !count1
# !count0 & count1 & !count2;
-- Node name is ':56' = 'count2'
-- Equation name is 'count2', location is LC8_C20, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = count0 & count1 & !count2
# !count1 & count2;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC5_C17;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC3_C21;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC5_C21;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC1_C21;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC2_C21;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC7_C21;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC4_C21;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC8_C21;
-- Node name is ':34'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = DFFE( count2, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is ':36'
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = DFFE( count1, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is ':38'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = DFFE( count0, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = DFFE( _EQ004, GLOBAL(!clk), VCC, VCC, VCC);
_EQ004 = _LC7_C17
# !_LC6_C17 & _LC8_C18
# !_LC6_C21 & _LC8_C18
# _LC6_C17 & !_LC6_C21
# _LC6_C17 & !_LC8_C18;
-- Node name is ':42'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = DFFE( _EQ005, GLOBAL(!clk), VCC, VCC, VCC);
_EQ005 = _LC7_C17
# !_LC6_C21 & _LC8_C18
# !_LC6_C17 & _LC8_C18
# !_LC6_C17 & !_LC6_C21;
-- Node name is ':44'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ006 = _LC7_C17 & _LC8_C18
# _LC6_C17 & _LC7_C17
# !_LC6_C21 & !_LC8_C18
# _LC6_C17 & !_LC6_C21
# !_LC6_C21 & _LC7_C17;
-- Node name is ':46'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = _LC7_C17
# _LC6_C17 & !_LC6_C21
# _LC6_C17 & !_LC8_C18
# !_LC6_C21 & !_LC8_C18
# !_LC6_C17 & _LC6_C21 & _LC8_C18;
-- Node name is ':48'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = DFFE( _EQ008, GLOBAL(!clk), VCC, VCC, VCC);
_EQ008 = _LC6_C21 & !_LC7_C17
# !_LC6_C17 & !_LC7_C17
# !_LC7_C17 & _LC8_C18
# !_LC6_C17 & !_LC8_C18;
-- Node name is ':50'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = DFFE( _EQ009, GLOBAL(!clk), VCC, VCC, VCC);
_EQ009 = _LC6_C17 & _LC6_C21 & !_LC7_C17
# !_LC6_C17 & !_LC8_C18
# !_LC7_C17 & !_LC8_C18
# !_LC6_C17 & !_LC6_C21 & !_LC7_C17;
-- Node name is ':52'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = DFFE( _EQ010, GLOBAL(!clk), VCC, VCC, VCC);
_EQ010 = _LC7_C17
# _LC6_C17
# _LC6_C21 & _LC8_C18
# !_LC6_C21 & !_LC8_C18;
-- Node name is ':54'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = DFFE( _EQ011, GLOBAL(!clk), VCC, VCC, VCC);
_EQ011 = !count2 & _LC4_C17;
-- Node name is '~409~1'
-- Equation name is '~409~1', location is LC1_C17, type is buried.
-- synthesized logic cell
_LC1_C17 = LCELL( _EQ012);
_EQ012 = flag1 & !switch
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