tiaoshi.rpt

消抖程序

hour11   =  data31;

-- Node name is 'hour12' 
-- Equation name is 'hour12', type is output 
hour12   =  data32;

-- Node name is 'hour13' 
-- Equation name is 'hour13', type is output 
hour13   =  data33;

-- Node name is 'hour20' 
-- Equation name is 'hour20', type is output 
hour20   =  data40;

-- Node name is 'hour21' 
-- Equation name is 'hour21', type is output 
hour21   =  data41;

-- Node name is 'hour22' 
-- Equation name is 'hour22', type is output 
hour22   =  data42;

-- Node name is 'hour23' 
-- Equation name is 'hour23', type is output 
hour23   =  data43;

-- Node name is 'sec10' 
-- Equation name is 'sec10', type is output 
sec10    =  data10;

-- Node name is 'sec11' 
-- Equation name is 'sec11', type is output 
sec11    =  data11;

-- Node name is 'sec12' 
-- Equation name is 'sec12', type is output 
sec12    =  data12;

-- Node name is 'sec13' 
-- Equation name is 'sec13', type is output 
sec13    =  data13;

-- Node name is 'sec20' 
-- Equation name is 'sec20', type is output 
sec20    =  data20;

-- Node name is 'sec21' 
-- Equation name is 'sec21', type is output 
sec21    =  data21;

-- Node name is 'sec22' 
-- Equation name is 'sec22', type is output 
sec22    =  data22;

-- Node name is 'sec23' 
-- Equation name is 'sec23', type is output 
sec23    =  data23;

-- Node name is '|LPM_ADD_SUB:55|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = LCELL( _EQ014);
  _EQ014 =  data10 &  data11;

-- Node name is '|LPM_ADD_SUB:55|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ015);
  _EQ015 =  data10 &  data11 &  data12;

-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ016);
  _EQ016 =  data20 &  data21;

-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C9', type is buried 
_LC6_C9  = LCELL( _EQ017);
  _EQ017 =  data20 &  data21 &  data22;

-- Node name is '|LPM_ADD_SUB:207|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ018);
  _EQ018 =  data30 &  data31;

-- Node name is '|LPM_ADD_SUB:207|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = LCELL( _EQ019);
  _EQ019 =  data30 &  data31 &  data32;

-- Node name is '|LPM_ADD_SUB:283|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ020);
  _EQ020 =  data40 &  data41;

-- Node name is '|LPM_ADD_SUB:283|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B20', type is buried 
_LC7_B20 = LCELL( _EQ021);
  _EQ021 =  data40 &  data41 &  data42;

-- Node name is ':40' 
-- Equation name is '_LC4_C22', type is buried 
!_LC4_C22 = _LC4_C22~NOT;
_LC4_C22~NOT = LCELL( _EQ022);
  _EQ022 = !count10 & !count11 &  flag2;

-- Node name is ':46' 
-- Equation name is '_LC2_A22', type is buried 
!_LC2_A22 = _LC2_A22~NOT;
_LC2_A22~NOT = LCELL( _EQ023);
  _EQ023 =  data11
         # !data13
         #  data12
         # !data10;

-- Node name is ':116' 
-- Equation name is '_LC1_C22', type is buried 
!_LC1_C22 = _LC1_C22~NOT;
_LC1_C22~NOT = LCELL( _EQ024);
  _EQ024 =  count10 & !count11 &  flag2;

-- Node name is ':122' 
-- Equation name is '_LC2_C9', type is buried 
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ025);
  _EQ025 =  data21
         # !data23
         #  data22
         # !data20;

-- Node name is ':192' 
-- Equation name is '_LC2_C22', type is buried 
!_LC2_C22 = _LC2_C22~NOT;
_LC2_C22~NOT = LCELL( _EQ026);
  _EQ026 = !count10 &  count11 &  flag2;

-- Node name is ':198' 
-- Equation name is '_LC2_C23', type is buried 
!_LC2_C23 = _LC2_C23~NOT;
_LC2_C23~NOT = LCELL( _EQ027);
  _EQ027 =  data31
         # !data33
         #  data32
         # !data30;

-- Node name is ':268' 
-- Equation name is '_LC3_C22', type is buried 
!_LC3_C22 = _LC3_C22~NOT;
_LC3_C22~NOT = LCELL( _EQ028);
  _EQ028 =  count10 &  count11 &  flag2;

-- Node name is ':274' 
-- Equation name is '_LC4_B20', type is buried 
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ029);
  _EQ029 =  data41
         # !data43
         #  data42
         # !data40;



Project Information                                         e:\eda\tiaoshi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,549K