xiaodou.vhd

消抖程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity xiaodou is
 port
	(  key_in     : in  std_logic;
	   clk        : in  std_logic;
       key_out    : out std_logic
            );
end entity;

architecture arc1 of xiaodou is

component diff
 port
	(  cp    : in  std_logic;
	   d     : in  std_logic;
       q     : out std_logic;
       qb    : out std_logic
     );
end component diff;

signal tmp1 : std_logic;
signal tmp2 : std_logic;
signal tmp3 : std_logic;
signal tmp4 : std_logic;
signal tmp5 : std_logic;
signal tmp6 : std_logic;

begin
tmp2<=key_in nand tmp1;

tmp1<=tmp3 nand tmp2;

key_out<=tmp4 and tmp5;

U1:diff
port map(clk,tmp2,tmp4,tmp3);
U2:diff
port map(clk,tmp4,tmp6,tmp5);

end arc1;


library ieee;
use ieee.std_logic_1164.all;
entity diff is
 port
	(  cp    : in  std_logic;
       d     : in  std_logic;
	   q     : out std_logic;
       qb    : out std_logic
     );
end entity;
architecture arc of diff is
begin
process(cp) is
begin
if(cp'event and cp='1')then
       q<=d;
      qb<=not d;
end if;
end process;
end arc;