📄 bianhuan.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bianhuan is
port
( up : in std_logic;
down : in std_logic;
flag : out std_logic;
clk : out std_logic
);
end entity;
architecture arc of bianhuan is
signal clk0 :std_logic:='0';
begin
process(up) is
begin
if(up'event and up='1')then
flag<='0';
clk0<=not clk0;
end if;
end process;
process(down) is
begin
if(down'event and down='1')then
flag<='1';
clk0<=not clk0;
end if;
end process;
clk<=clk0;
end arc;
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