cic_4_dec.v

实现4倍抽取的CIC抽取滤波器模块的Verilog实现

module cic_4_dec(clk,reset,cic_in,cic_out,rdy);
    input clk;
    input reset;
    input [15:0] cic_in;
    output [39:0] cic_out;
    output rdy;
    reg [39:0] integrator1=0;
    reg [39:0] integrator2=0;
    reg [39:0] integrator3=0;
    reg [39:0] integrator4=0;
    reg [39:0] integrator5=0;
    reg [39:0] decimator1=0;
    reg [39:0] decimator1_z=0;
    reg [39:0] decimator2=0;
    reg [39:0] decimator2_z=0;
    reg [39:0] decimator3=0;
    reg [39:0] decimator3_z=0;
    reg [39:0] decimator4=0;
    reg [39:0] decimator4_z=0;
    reg [39:0] decimator5=0;
    reg [39:0] decimator5_z=0;
    reg [39:0] cic_out=0;
    reg rdy;
    reg [39:0] cic=0;
    reg [7:0] counter=0;
    
    always@ (posedge clk or posedge reset)
    begin
        if(reset)
        begin
            cic<=0;
            integrator1<=0;
            integrator2<=0;
            integrator3<=0;
            integrator4<=0;
            integrator5<=0;
            counter<=0;
        end
        else
        begin
            cic[39:16]<={24{cic_in[15]}};
            cic[15:0]<=cic_in[15:0];
            integrator1<=cic+integrator1;
            integrator2<=integrator1+integrator2;
            integrator3<=integrator2+integrator3;
            integrator4<=integrator3+integrator4;
            integrator5<=integrator4+integrator5;
            counter<=counter+1;
            if(counter==3)
            begin
                counter<=0;
                decimator1<=integrator5;
                decimator1_z<=decimator1;
                decimator2<=decimator1-decimator1_z;
                decimator2_z<=decimator2;
                decimator3<=decimator2-decimator2_z;
                decimator3_z<=decimator3;
                decimator4<=decimator3-decimator3_z;
                decimator4_z<=decimator4;
                decimator5<=decimator4-decimator4_z;
                decimator5_z<=decimator5;
                rdy<=1;
            end
            if(rdy)
            rdy<=0;
        end
    end
endmodule