jfqs_multiplier.map.rpt

使用加法器树乘法器实现8位乘法运算

; high_zero.vhd                    ; yes             ; User VHDL File  ; C:/altera/quartus50/myq2projects/jfqs_multiplier/high_zero.vhd       ;
; add2.vhd                         ; yes             ; User VHDL File  ; C:/altera/quartus50/myq2projects/jfqs_multiplier/add2.vhd            ;
; jfqs_multiplier.vhd              ; yes             ; User VHDL File  ; C:/altera/quartus50/myq2projects/jfqs_multiplier/jfqs_multiplier.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 147     ;
; Total combinational functions     ; 128     ;
;     -- Total 4-input functions    ; 0       ;
;     -- Total 3-input functions    ; 0       ;
;     -- Total 2-input functions    ; 116     ;
;     -- Total 1-input functions    ; 8       ;
;     -- Total 0-input functions    ; 4       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 32      ;
; Total logic cells in carry chains ; 68      ;
; I/O pins                          ; 33      ;
; Maximum fan-out node              ; clock   ;
; Maximum fan-out                   ; 32      ;
; Total fan-out                     ; 368     ;
; Average fan-out                   ; 2.04    ;
+-----------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; |jfqs_multiplier           ; 147 (32)    ; 32           ; 0           ; 33   ; 0            ; 115 (0)      ; 19 (19)           ; 13 (13)          ; 68 (12)         ; |jfqs_multiplier             ;
;    |add1:U10|              ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; |jfqs_multiplier|add1:U10    ;
;    |add1:U13|              ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; |jfqs_multiplier|add1:U13    ;
;    |add1:U16|              ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; |jfqs_multiplier|add1:U16    ;
;    |add1:U19|              ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 9 (9)           ; |jfqs_multiplier|add1:U19    ;
;    |add2:U20|              ; 10 (10)     ; 0            ; 0           ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; |jfqs_multiplier|add2:U20    ;
;    |add2:U21|              ; 10 (10)     ; 0            ; 0           ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; |jfqs_multiplier|add2:U21    ;
;    |and_mode:U0|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U0 ;
;    |and_mode:U1|           ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U1 ;
;    |and_mode:U2|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U2 ;
;    |and_mode:U3|           ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U3 ;
;    |and_mode:U4|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U4 ;
;    |and_mode:U5|           ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U5 ;
;    |and_mode:U6|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U6 ;
;    |and_mode:U7|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |jfqs_multiplier|and_mode:U7 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 32    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/myq2projects/jfqs_multiplier/jfqs_multiplier.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 20 23:21:48 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jfqs_multiplier -c jfqs_multiplier
Info: Found 2 design units, including 1 entities, in source file add1.vhd
    Info: Found design unit 1: add1-answer1
    Info: Found entity 1: add1
Info: Found 2 design units, including 1 entities, in source file and_mode.vhd
    Info: Found design unit 1: and_mode-answer2
    Info: Found entity 1: and_mode
Info: Found 2 design units, including 1 entities, in source file low_zero.vhd
    Info: Found design unit 1: low_zero-answer3
    Info: Found entity 1: low_zero
Info: Found 2 design units, including 1 entities, in source file high_zero.vhd
    Info: Found design unit 1: high_zero-answer4
    Info: Found entity 1: high_zero
Info: Found 2 design units, including 1 entities, in source file add2.vhd
    Info: Found design unit 1: add2-answer5
    Info: Found entity 1: add2
Info: Found 2 design units, including 1 entities, in source file jfqs_multiplier.vhd
    Info: Found design unit 1: jfqs_multiplier-answer
    Info: Found entity 1: jfqs_multiplier
Info: Elaborating entity "jfqs_multiplier" for the top level hierarchy
Info: Elaborating entity "and_mode" for hierarchy "and_mode:U0"
Info: Elaborating entity "low_zero" for hierarchy "low_zero:U8"
Info: Elaborating entity "high_zero" for hierarchy "high_zero:U9"
Info: Elaborating entity "add1" for hierarchy "add1:U10"
Warning: VHDL Process Statement warning at add1.vhd(22): signal "l1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at add1.vhd(22): signal "l2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "add2" for hierarchy "add2:U20"
Info: Implemented 180 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 16 output pins
    Info: Implemented 147 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jun 20 23:21:51 2008
    Info: Elapsed time: 00:00:03