📄 xor_mul.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register c\[4\] m\[4\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"c\[4\]\" and destination register \"m\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.026 ns + Longest register register " "Info: + Longest register to register delay is 2.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c\[4\] 1 REG LC_X11_Y17_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y17_N3; Fanout = 1; REG Node = 'c\[4\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { c[4] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.288 ns) + CELL(0.738 ns) 2.026 ns m\[4\] 2 REG LC_X12_Y16_N6 1 " "Info: 2: + IC(1.288 ns) + CELL(0.738 ns) = 2.026 ns; Loc. = LC_X12_Y16_N6; Fanout = 1; REG Node = 'm\[4\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.026 ns" { c[4] m[4] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 36.43 % " "Info: Total cell delay = 0.738 ns ( 36.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.288 ns 63.57 % " "Info: Total interconnect delay = 1.288 ns ( 63.57 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.026 ns" { c[4] m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.026 ns" { c[4] m[4] } { 0.000ns 1.288ns } { 0.000ns 0.738ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { clk } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns m\[4\] 2 REG LC_X12_Y16_N6 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y16_N6; Fanout = 1; REG Node = 'm\[4\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "1.485 ns" { clk m[4] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 m[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { clk } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns c\[4\] 2 REG LC_X11_Y17_N3 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y17_N3; Fanout = 1; REG Node = 'c\[4\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "1.485 ns" { clk c[4] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 m[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 17 -1 0 } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.026 ns" { c[4] m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.026 ns" { c[4] m[4] } { 0.000ns 1.288ns } { 0.000ns 0.738ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 m[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { m[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { m[4] } { } { } } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 17 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "c\[6\] b\[2\] clk 8.022 ns register " "Info: tsu for register \"c\[6\]\" (data pin = \"b\[2\]\", clock pin = \"clk\") is 8.022 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.939 ns + Longest pin register " "Info: + Longest pin to register delay is 10.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[2\] 1 PIN PIN_228 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 8; PIN Node = 'b\[2\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { b[2] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.604 ns) + CELL(0.590 ns) 8.669 ns c~840 2 COMB LC_X11_Y17_N8 1 " "Info: 2: + IC(6.604 ns) + CELL(0.590 ns) = 8.669 ns; Loc. = LC_X11_Y17_N8; Fanout = 1; COMB Node = 'c~840'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "7.194 ns" { b[2] c~840 } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.532 ns) + CELL(0.738 ns) 10.939 ns c\[6\] 3 REG LC_X13_Y16_N3 1 " "Info: 3: + IC(1.532 ns) + CELL(0.738 ns) = 10.939 ns; Loc. = LC_X13_Y16_N3; Fanout = 1; REG Node = 'c\[6\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.270 ns" { c~840 c[6] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.803 ns 25.62 % " "Info: Total cell delay = 2.803 ns ( 25.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.136 ns 74.38 % " "Info: Total interconnect delay = 8.136 ns ( 74.38 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "10.939 ns" { b[2] c~840 c[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.939 ns" { b[2] b[2]~out0 c~840 c[6] } { 0.000ns 0.000ns 6.604ns 1.532ns } { 0.000ns 1.475ns 0.590ns 0.738ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { clk } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns c\[6\] 2 REG LC_X13_Y16_N3 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N3; Fanout = 1; REG Node = 'c\[6\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "1.485 ns" { clk c[6] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "10.939 ns" { b[2] c~840 c[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.939 ns" { b[2] b[2]~out0 c~840 c[6] } { 0.000ns 0.000ns 6.604ns 1.532ns } { 0.000ns 1.475ns 0.590ns 0.738ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk product\[5\] product\[5\]~reg0 7.855 ns register " "Info: tco from clock \"clk\" to destination pin \"product\[5\]\" through register \"product\[5\]~reg0\" is 7.855 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { clk } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns product\[5\]~reg0 2 REG LC_X13_Y16_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y16_N2; Fanout = 1; REG Node = 'product\[5\]~reg0'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "1.485 ns" { clk product[5]~reg0 } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk product[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 product[5]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.677 ns + Longest register pin " "Info: + Longest register to pin delay is 4.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns product\[5\]~reg0 1 REG LC_X13_Y16_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N2; Fanout = 1; REG Node = 'product\[5\]~reg0'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { product[5]~reg0 } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.553 ns) + CELL(2.124 ns) 4.677 ns product\[5\] 2 PIN PIN_11 0 " "Info: 2: + IC(2.553 ns) + CELL(2.124 ns) = 4.677 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'product\[5\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "4.677 ns" { product[5]~reg0 product[5] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.41 % " "Info: Total cell delay = 2.124 ns ( 45.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.553 ns 54.59 % " "Info: Total interconnect delay = 2.553 ns ( 54.59 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "4.677 ns" { product[5]~reg0 product[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.677 ns" { product[5]~reg0 product[5] } { 0.000ns 2.553ns } { 0.000ns 2.124ns } } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk product[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 product[5]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "4.677 ns" { product[5]~reg0 product[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.677 ns" { product[5]~reg0 product[5] } { 0.000ns 2.553ns } { 0.000ns 2.124ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "c\[0\] a\[0\] clk -0.721 ns register " "Info: th for register \"c\[0\]\" (data pin = \"a\[0\]\", clock pin = \"clk\") is -0.721 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { clk } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns c\[0\] 2 REG LC_X11_Y16_N6 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y16_N6; Fanout = 1; REG Node = 'c\[0\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "1.485 ns" { clk c[0] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.690 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns a\[0\] 1 PIN PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; PIN Node = 'a\[0\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "" { a[0] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.912 ns) + CELL(0.309 ns) 3.690 ns c\[0\] 2 REG LC_X11_Y16_N6 1 " "Info: 2: + IC(1.912 ns) + CELL(0.309 ns) = 3.690 ns; Loc. = LC_X11_Y16_N6; Fanout = 1; REG Node = 'c\[0\]'" { } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.221 ns" { a[0] c[0] } "NODE_NAME" } "" } } { "xor_mul.vhd" "" { Text "C:/altera/quartus50/myq2projects/xor_mul/xor_mul.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 48.18 % " "Info: Total cell delay = 1.778 ns ( 48.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns 51.82 % " "Info: Total interconnect delay = 1.912 ns ( 51.82 % )" { } { } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "3.690 ns" { a[0] c[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.690 ns" { a[0] a[0]~out0 c[0] } { 0.000ns 0.000ns 1.912ns } { 0.000ns 1.469ns 0.309ns } } } } 0} } { { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "2.954 ns" { clk c[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 c[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" "" { Report "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul_cmp.qrpt" Compiler "xor_mul" "UNKNOWN" "V1" "C:/altera/quartus50/myq2projects/xor_mul/db/xor_mul.quartus_db" { Floorplan "C:/altera/quartus50/myq2projects/xor_mul/" "" "3.690 ns" { a[0] c[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.690 ns" { a[0] a[0]~out0 c[0] } { 0.000ns 0.000ns 1.912ns } { 0.000ns 1.469ns 0.309ns } } } } 0}
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