📄 xor_mul.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor_mul is
port(
a,b : in std_logic_vector (7 downto 0);
clk : in std_logic;
product: out std_logic_vector (7 downto 0)
);
end xor_mul;
architecture answer of xor_mul is
signal c : std_logic_vector (14 downto 0);
signal m : std_logic_vector (7 downto 0);
begin
process ( clk, a, b )
begin
if clk'event and clk='1' then
c(14)<=a(7) and b(7);
c(13)<=(a(7) and b(6)) xor (a(6) and b(7));
c(12)<=(a(7) and b(5)) xor (a(6) and b(6)) xor (a(5) and b(7));
c(11)<=(a(7) and b(4)) xor (a(6) and b(5)) xor (a(5) and b(6)) xor (a(4) and b(7));
c(10)<=(a(7) and b(3)) xor (a(6) and b(4)) xor (a(5) and b(5)) xor (a(4) and b(6)) xor (a(3) and b(7));
c(9)<=(a(7) and b(2)) xor (a(6) and b(3)) xor (a(5) and b(4)) xor (a(4) and b(5)) xor (a(3) and b(6)) xor (a(2) and b(7));
c(8)<=(a(7) and b(1)) xor (a(6) and b(2)) xor (a(5) and b(3)) xor (a(4) and b(4)) xor (a(3) and b(5)) xor (a(2) and b(6)) xor (a(1) and b(7));
c(7)<=(a(7) and b(0)) xor (a(6) and b(1)) xor (a(5) and b(2)) xor (a(4) and b(3)) xor (a(3) and b(4)) xor (a(2) and b(5)) xor (a(1) and b(6)) xor (a(0) and b(7));
c(6)<=(a(6) and b(0)) xor (a(5) and b(1)) xor (a(4) and b(2)) xor (a(3) and b(3)) xor (a(2) and b(4)) xor (a(1) and b(5)) xor (a(0) and b(6));
c(5)<=(a(5) and b(0)) xor (a(4) and b(1)) xor (a(3) and b(2)) xor (a(2) and b(3)) xor (a(1) and b(4)) xor (a(0) and b(5));
c(4)<=(a(4) and b(0)) xor (a(3) and b(1)) xor (a(2) and b(2)) xor (a(1) and b(3)) xor (a(0) and b(4));
c(3)<=(a(3) and b(0)) xor (a(2) and b(1)) xor (a(1) and b(2)) xor (a(0) and b(3));
c(2)<=(a(2) and b(0)) xor (a(1) and b(1)) xor (a(0) and b(2));
c(1)<=(a(1) and b(0)) xor (a(0) and b(1));
c(0)<=a(0) and b(0);
m(7)<=c(7) xor c(11) xor c(12) xor c(14);
m(6)<=c(6) xor c(10) xor c(11) xor c(13);
m(5)<=c(5) xor c(9) xor c(10) xor c(12);
m(4)<=c(4) xor c(8) xor c(9) xor c(11) xor c(14);
m(3)<=c(3) xor c(8) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14);
m(2)<=c(2) xor c(9) xor c(10) xor c(13);
m(1)<=c(1) xor c(8) xor c(9) xor c(12) xor c(14);
m(0)<=c(0) xor c(8) xor c(12) xor c(13);
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
product<=m;
end if;
end process;
end answer;
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