buff.vhd

来自「用VHDL实现频率计」· VHDL 代码 · 共 33 行

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY BUFF IS

	PORT
	(
		LD		: IN	STD_LOGIC;
		AA			: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		BB			: OUT 	STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
	
END BUFF;

ARCHITECTURE a OF BUFF IS
SIGNAL BUFF1: STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
PROCESS(LD)
BEGIN
IF LD='1' THEN BUFF1<=AA;
ELSE NULL;
END IF;
END PROCESS;
BB<=BUFF1;
END A;