led.vhd

用VHDL实现频率计

library ieee;
use ieee.std_logic_1164.all;
entity led is
port( datain:IN std_logic_vector(3 downto 0);
dataout:OUT std_logic_vector(6 downto 0));
end led;
architecture one of led is
begin
process(datain)
begin
case datain is
when "0000" => dataout<="0111111";
when "0001" => dataout<="0000110";
when "0010" => dataout<="1011011";
when "0011" => dataout<="1001111";
when "0100" => dataout<="1100110";
when "0101" => dataout<="1101101";
when "0110" => dataout<="1111101";
when "0111" => dataout<="0000111";
when "1000" => dataout<="1111111";
when "1001" => dataout<="1101111";
when "1010" => dataout<="1110111";
when "1011" => dataout<="1111100";
when "1100" => dataout<="0111001";
when "1101" => dataout<="1011110";
when "1110" => dataout<="1111001";
when "1111" => dataout<="1110001";
when OTHERS=> NULL;
end case;
end process;
end one;