control.vhd

用VHDL实现频率计

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY contrOl IS

	PORT
	(
		clk				: IN	STD_LOGIC;
		EN,LD,RST		: OUT 	STD_LOGIC
	);
	
END contrOl;

ARCHITECTURE a OF contrOl IS
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    	LD<='1' 		WHEN 	Q="1010"    ELSE '0';
  		RST<='1'		WHEN	Q="1100"    ELSE '0';
  
PROCESS (CLK)
BEGIN
IF clk'EVENT AND clk = '1'THEN
     Q<=Q+1;
     EN<=not Q(3);
END IF;
END PROCESS;
END A;