main.rpt

用VHDL实现频率计

-- Equation name is '_LC072', type is buried 
_LC072   = DFFE( _LC074 $  GND,  _EQ041,  VCC,  VCC,  VCC);
  _EQ041 = !_LC050 &  _LC052 & !_LC054 &  _LC055;

-- Node name is '|BUFF:U9|:12' = '|BUFF:U9|BUFF11' 
-- Equation name is '_LC075', type is buried 
_LC075   = DFFE( _LC079 $  GND,  _EQ042,  VCC,  VCC,  VCC);
  _EQ042 = !_LC050 &  _LC052 & !_LC054 &  _LC055;

-- Node name is '|BUFF:U9|:11' = '|BUFF:U9|BUFF12' 
-- Equation name is '_LC065', type is buried 
_LC065   = DFFE( _LC073 $  GND,  _EQ043,  VCC,  VCC,  VCC);
  _EQ043 = !_LC050 &  _LC052 & !_LC054 &  _LC055;

-- Node name is '|BUFF:U9|:10' = '|BUFF:U9|BUFF13' 
-- Equation name is '_LC067', type is buried 
_LC067   = DFFE( _LC078 $  GND,  _EQ044,  VCC,  VCC,  VCC);
  _EQ044 = !_LC050 &  _LC052 & !_LC054 &  _LC055;

-- Node name is '|cnt10:U2|:14' = '|cnt10:U2|CQI0' 
-- Equation name is '_LC087', type is buried 
_LC087   = DFFE( _EQ045 $  GND,  FIN, !_EQ046,  VCC,  VCC);
  _EQ045 =  _LC056 &  _LC086 & !_LC087 & !_LC088 & !_LC089
         #  _LC056 & !_LC086 & !_LC087
         # !_LC056 &  _LC087;
  _EQ046 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U2|:13' = '|cnt10:U2|CQI1' 
-- Equation name is '_LC089', type is buried 
_LC089   = DFFE( _EQ047 $  GND,  FIN, !_EQ048,  VCC,  VCC);
  _EQ047 =  _LC056 & !_LC086 & !_LC087 &  _LC089
         #  _LC056 & !_LC086 &  _LC087 & !_LC089
         # !_LC056 &  _LC089;
  _EQ048 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U2|:12' = '|cnt10:U2|CQI2' 
-- Equation name is '_LC088', type is buried 
_LC088   = TFFE( _EQ049,  FIN, !_EQ050,  VCC,  VCC);
  _EQ049 =  _LC056 & !_LC086 &  _LC087 & !_LC088 &  _LC089
         #  _LC056 &  _LC087 &  _LC088 &  _LC089
         #  _LC056 &  _LC086 &  _LC088;
  _EQ050 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U2|:11' = '|cnt10:U2|CQI3' 
-- Equation name is '_LC086', type is buried 
_LC086   = DFFE( _EQ051 $  GND,  FIN, !_EQ052,  VCC,  VCC);
  _EQ051 =  _LC056 &  _LC086 & !_LC087 & !_LC088 & !_LC089 &  _X001
         #  _LC056 & !_LC086 &  _LC087 &  _LC088 &  _LC089
         # !_LC056 &  _LC086;
  _X001  = EXP( _LC087 &  _LC088 &  _LC089);
  _EQ052 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U3|:14' = '|cnt10:U3|CQI0' 
-- Equation name is '_LC093', type is buried 
_LC093   = DFFE( _EQ053 $  GND,  _EQ054, !_EQ055,  VCC,  VCC);
  _EQ053 =  _LC056 & !_LC092 & !_LC093 & !_LC094 &  _LC096
         #  _LC056 & !_LC093 & !_LC096
         # !_LC056 &  _LC093;
  _EQ054 =  _LC086 &  _LC087 & !_LC088 & !_LC089;
  _EQ055 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U3|:13' = '|cnt10:U3|CQI1' 
-- Equation name is '_LC092', type is buried 
_LC092   = DFFE( _EQ056 $  GND,  _EQ057, !_EQ058,  VCC,  VCC);
  _EQ056 =  _LC056 &  _LC092 & !_LC093 & !_LC096
         #  _LC056 & !_LC092 &  _LC093 & !_LC096
         # !_LC056 &  _LC092;
  _EQ057 =  _LC086 &  _LC087 & !_LC088 & !_LC089;
  _EQ058 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U3|:12' = '|cnt10:U3|CQI2' 
-- Equation name is '_LC094', type is buried 
_LC094   = TFFE( _EQ059,  _EQ060, !_EQ061,  VCC,  VCC);
  _EQ059 =  _LC056 &  _LC092 &  _LC093 & !_LC094 & !_LC096
         #  _LC056 &  _LC092 &  _LC093 &  _LC094
         #  _LC056 &  _LC094 &  _LC096;
  _EQ060 =  _LC086 &  _LC087 & !_LC088 & !_LC089;
  _EQ061 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U3|:11' = '|cnt10:U3|CQI3' 
-- Equation name is '_LC096', type is buried 
_LC096   = DFFE( _EQ062 $  GND,  _EQ063, !_EQ064,  VCC,  VCC);
  _EQ062 =  _LC056 & !_LC092 & !_LC093 & !_LC094 &  _LC096 &  _X002
         #  _LC056 &  _LC092 &  _LC093 &  _LC094 & !_LC096
         # !_LC056 &  _LC096;
  _X002  = EXP( _LC092 &  _LC093 &  _LC094);
  _EQ063 =  _LC086 &  _LC087 & !_LC088 & !_LC089;
  _EQ064 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U4|:14' = '|cnt10:U4|CQI0' 
-- Equation name is '_LC090', type is buried 
_LC090   = DFFE( _EQ065 $  GND,  _EQ066, !_EQ067,  VCC,  VCC);
  _EQ065 =  _LC056 & !_LC082 & !_LC085 & !_LC090 &  _LC091
         #  _LC056 & !_LC090 & !_LC091
         # !_LC056 &  _LC090;
  _EQ066 = !_LC092 &  _LC093 & !_LC094 &  _LC096;
  _EQ067 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U4|:13' = '|cnt10:U4|CQI1' 
-- Equation name is '_LC082', type is buried 
_LC082   = DFFE( _EQ068 $  GND,  _EQ069, !_EQ070,  VCC,  VCC);
  _EQ068 =  _LC056 &  _LC082 & !_LC090 & !_LC091
         #  _LC056 & !_LC082 &  _LC090 & !_LC091
         # !_LC056 &  _LC082;
  _EQ069 = !_LC092 &  _LC093 & !_LC094 &  _LC096;
  _EQ070 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U4|:12' = '|cnt10:U4|CQI2' 
-- Equation name is '_LC085', type is buried 
_LC085   = TFFE( _EQ071,  _EQ072, !_EQ073,  VCC,  VCC);
  _EQ071 =  _LC056 &  _LC082 & !_LC085 &  _LC090 & !_LC091
         #  _LC056 &  _LC082 &  _LC085 &  _LC090
         #  _LC056 &  _LC085 &  _LC091;
  _EQ072 = !_LC092 &  _LC093 & !_LC094 &  _LC096;
  _EQ073 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U4|:11' = '|cnt10:U4|CQI3' 
-- Equation name is '_LC091', type is buried 
_LC091   = DFFE( _EQ074 $  GND,  _EQ075, !_EQ076,  VCC,  VCC);
  _EQ074 =  _LC056 & !_LC082 & !_LC085 & !_LC090 &  _LC091 &  _X003
         #  _LC056 &  _LC082 &  _LC085 &  _LC090 & !_LC091
         # !_LC056 &  _LC091;
  _X003  = EXP( _LC082 &  _LC085 &  _LC090);
  _EQ075 = !_LC092 &  _LC093 & !_LC094 &  _LC096;
  _EQ076 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U5|:14' = '|cnt10:U5|CQI0' 
-- Equation name is '_LC074', type is buried 
_LC074   = DFFE( _EQ077 $  GND,  _EQ078, !_EQ079,  VCC,  VCC);
  _EQ077 =  _LC056 & !_LC073 & !_LC074 &  _LC078 & !_LC079
         #  _LC056 & !_LC074 & !_LC078
         # !_LC056 &  _LC074;
  _EQ078 = !_LC082 & !_LC085 &  _LC090 &  _LC091;
  _EQ079 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U5|:13' = '|cnt10:U5|CQI1' 
-- Equation name is '_LC079', type is buried 
_LC079   = DFFE( _EQ080 $  GND,  _EQ081, !_EQ082,  VCC,  VCC);
  _EQ080 =  _LC056 & !_LC074 & !_LC078 &  _LC079
         #  _LC056 &  _LC074 & !_LC078 & !_LC079
         # !_LC056 &  _LC079;
  _EQ081 = !_LC082 & !_LC085 &  _LC090 &  _LC091;
  _EQ082 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U5|:12' = '|cnt10:U5|CQI2' 
-- Equation name is '_LC073', type is buried 
_LC073   = TFFE( _EQ083,  _EQ084, !_EQ085,  VCC,  VCC);
  _EQ083 =  _LC056 & !_LC073 &  _LC074 & !_LC078 &  _LC079
         #  _LC056 &  _LC073 &  _LC074 &  _LC079
         #  _LC056 &  _LC073 &  _LC078;
  _EQ084 = !_LC082 & !_LC085 &  _LC090 &  _LC091;
  _EQ085 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|cnt10:U5|:11' = '|cnt10:U5|CQI3' 
-- Equation name is '_LC078', type is buried 
_LC078   = DFFE( _EQ086 $  GND,  _EQ087, !_EQ088,  VCC,  VCC);
  _EQ086 =  _LC056 & !_LC073 & !_LC074 &  _LC078 & !_LC079 &  _X004
         #  _LC056 &  _LC073 &  _LC074 & !_LC078 &  _LC079
         # !_LC056 &  _LC078;
  _X004  = EXP( _LC073 &  _LC074 &  _LC079);
  _EQ087 = !_LC082 & !_LC085 &  _LC090 &  _LC091;
  _EQ088 = !_LC050 &  _LC052 &  _LC054 & !_LC055;

-- Node name is '|contrOl:U1|:9' = '|contrOl:U1|Q0' 
-- Equation name is '_LC050', type is buried 
_LC050   = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|contrOl:U1|:8' = '|contrOl:U1|Q1' 
-- Equation name is '_LC055', type is buried 
_LC055   = TFFE( _LC050, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|contrOl:U1|:7' = '|contrOl:U1|Q2' 
-- Equation name is '_LC054', type is buried 
_LC054   = TFFE( _EQ089, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ089 =  _LC050 &  _LC055;

-- Node name is '|contrOl:U1|:6' = '|contrOl:U1|Q3' 
-- Equation name is '_LC052', type is buried 
_LC052   = TFFE( _EQ090, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ090 =  _LC050 &  _LC054 &  _LC055;

-- Node name is '|contrOl:U1|:2' 
-- Equation name is '_LC056', type is buried 
_LC056   = DFFE(!_LC052 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          d:\frudh\main.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,529K