clkgen.rpt

vhdl语言编写秒表程序 内含每个模块的源程序

 (36)    22    B       TFFE   +  t        0      0   0    0    6    1   10  CNTER0 (:8)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\eda-bill\clkgen.rpt
clkgen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC27 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node1
        | +------------------- LC26 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
        | | +----------------- LC25 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
        | | | +--------------- LC24 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
        | | | | +------------- LC23 NEWCLK
        | | | | | +----------- LC21 CNTER5
        | | | | | | +--------- LC20 CNTER4
        | | | | | | | +------- LC19 CNTER3
        | | | | | | | | +----- LC18 CNTER2
        | | | | | | | | | +--- LC17 CNTER1
        | | | | | | | | | | +- LC22 CNTER0
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node1
LC26 -> - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
LC25 -> - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
LC24 -> - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
LC21 -> - - - * * * * * - * * | - * | <-- CNTER5
LC20 -> - - * * * * * * - * * | - * | <-- CNTER4
LC19 -> - * * * * * * * - * * | - * | <-- CNTER3
LC18 -> - * * * * * * * * * * | - * | <-- CNTER2
LC17 -> * * * * * * * * * * * | - * | <-- CNTER1
LC22 -> * * * * * * * * * * * | - * | <-- CNTER0

Pin
43   -> - - - - - - - - - - - | - - | <-- CLK


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda-bill\clkgen.rpt
clkgen

** EQUATIONS **

CLK      : INPUT;

-- Node name is ':8' = 'CNTER0' 
-- Equation name is 'CNTER0', location is LC022, type is buried.
CNTER0   = TFFE(!_EQ001, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ001 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5;

-- Node name is ':7' = 'CNTER1' 
-- Equation name is 'CNTER1', location is LC017, type is buried.
CNTER1   = DFFE( _EQ002 $  _LC027, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5 & 
              _LC027;

-- Node name is ':6' = 'CNTER2' 
-- Equation name is 'CNTER2', location is LC018, type is buried.
CNTER2   = TFFE( _EQ003, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  CNTER0 &  CNTER1;

-- Node name is ':5' = 'CNTER3' 
-- Equation name is 'CNTER3', location is LC019, type is buried.
CNTER3   = DFFE( _EQ004 $  _LC026, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5 & 
              _LC026;

-- Node name is ':4' = 'CNTER4' 
-- Equation name is 'CNTER4', location is LC020, type is buried.
CNTER4   = DFFE( _EQ005 $  _LC025, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ005 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5 & 
              _LC025;

-- Node name is ':3' = 'CNTER5' 
-- Equation name is 'CNTER5', location is LC021, type is buried.
CNTER5   = DFFE( _EQ006 $  _LC024, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ006 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5 & 
              _LC024;

-- Node name is 'NEWCLK' 
-- Equation name is 'NEWCLK', location is LC023, type is output.
 NEWCLK  = LCELL( _EQ007 $  GND);
  _EQ007 = !CNTER0 &  CNTER1 & !CNTER2 & !CNTER3 &  CNTER4 &  CNTER5;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( CNTER1 $  CNTER0);

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( CNTER3 $  _EQ008);
  _EQ008 =  CNTER0 &  CNTER1 &  CNTER2;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( CNTER4 $  _EQ009);
  _EQ009 =  CNTER0 &  CNTER1 &  CNTER2 &  CNTER3;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( CNTER5 $  _EQ010);
  _EQ010 =  CNTER0 &  CNTER1 &  CNTER2 &  CNTER3 &  CNTER4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     d:\eda-bill\clkgen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,923K