cnt6.vhd

来自「vhdl语言编写秒表程序 内含每个模块的源程序」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT (CLK:IN STD_LOGIC;
      CLR:IN STD_LOGIC;
      ENA:IN STD_LOGIC;
       CQ:OUT STD_LOGIC_VECTOR(3 TO 0);
CARRY_OUT:OUT STD_LOGIC );
END CNT6;
ARCHITECTURE ART OF CNT6 IS
SIGNAL CQI:STD_LOGIC_VECTOR(3 TO 0);
BEGIN
PROCESS(CLK,CLR,ENA)
BEGIN
   IF CLR='1' THEN CQI<="0000";
   ELSIF CLK'EVENT AND CLK='1' THEN
      IF ENA='1' THEN
         IF CQI="0101" THEN CQI<="0000";
         ELSE CQI<=CQI+'1'; END IF;
      END IF;
     END IF;
   END PROCESS;
   PROCESS(CQI)
   BEGIN
      IF CQI="0000" THEN CARRY_OUT<='1';
         ELSE CARRY_OUT<='0'; END IF;
   END PROCESS;
   CQ<=CQI;
END ART;