📄 clock1.rpt
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_LC058 & _LC059 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:12' = '|CLKGEN:1|CNTER5'
-- Equation name is '_LC004', type is buried
_LC004 = DFFE( _EQ046 $ _LC055, GLOBAL( CLK), VCC, VCC, VCC);
_EQ046 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC055 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:11' = '|CLKGEN:1|CNTER6'
-- Equation name is '_LC011', type is buried
_LC011 = DFFE( _EQ047 $ _LC012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ047 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC012 &
_LC018 & !_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 &
_LC029 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:10' = '|CLKGEN:1|CNTER7'
-- Equation name is '_LC009', type is buried
_LC009 = DFFE( _EQ048 $ _LC043, GLOBAL( CLK), VCC, VCC, VCC);
_EQ048 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC043 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:9' = '|CLKGEN:1|CNTER8'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ049 $ _LC038, GLOBAL( CLK), VCC, VCC, VCC);
_EQ049 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC038 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:8' = '|CLKGEN:1|CNTER9'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ050 $ _LC039, GLOBAL( CLK), VCC, VCC, VCC);
_EQ050 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC039 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:7' = '|CLKGEN:1|CNTER10'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _EQ051 $ _LC042, GLOBAL( CLK), VCC, VCC, VCC);
_EQ051 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC042 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:6' = '|CLKGEN:1|CNTER11'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ052 $ _LC044, GLOBAL( CLK), VCC, VCC, VCC);
_EQ052 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC044 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:5' = '|CLKGEN:1|CNTER12'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _EQ053 $ _LC045, GLOBAL( CLK), VCC, VCC, VCC);
_EQ053 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC045 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:4' = '|CLKGEN:1|CNTER13'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ054 $ _LC003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ054 = !_LC002 & _LC003 & _LC004 & _LC008 & !_LC009 & !_LC011 &
_LC018 & !_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 &
_LC029 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|:3' = '|CLKGEN:1|CNTER14'
-- Equation name is '_LC028', type is buried
_LC028 = DFFE( _EQ055 $ _LC031, GLOBAL( CLK), VCC, VCC, VCC);
_EQ055 = !_LC002 & _LC004 & _LC008 & !_LC009 & !_LC011 & _LC018 &
!_LC022 & !_LC023 & _LC026 & _LC027 & _LC028 & _LC029 &
_LC031 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( _LC008 $ _EQ056);
_EQ056 = _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC059', type is buried
_LC059 = LCELL( _LC002 $ _EQ057);
_EQ057 = _LC008 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( _LC004 $ _EQ058);
_EQ058 = _LC002 & _LC008 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( _LC011 $ _EQ059);
_EQ059 = _LC002 & _LC004 & _LC008 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried
_LC043 = LCELL( _LC009 $ _EQ060);
_EQ060 = _LC002 & _LC004 & _LC008 & _LC011 & _LC058 & _LC061 &
_LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC038', type is buried
_LC038 = LCELL( _LC026 $ _EQ061);
_EQ061 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC058 &
_LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC039', type is buried
_LC039 = LCELL( _LC023 $ _EQ062);
_EQ062 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC026 &
_LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried
_LC042 = LCELL( _LC027 $ _EQ063);
_EQ063 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC023 &
_LC026 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried
_LC044 = LCELL( _LC022 $ _EQ064);
_EQ064 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC023 &
_LC026 & _LC027 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried
_LC045 = LCELL( _LC018 $ _EQ065);
_EQ065 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC022 &
_LC023 & _LC026 & _LC027 & _LC058 & _LC061 & _LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC003', type is buried
_LC003 = LCELL( _LC029 $ _EQ066);
_EQ066 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC018 &
_LC022 & _LC023 & _LC026 & _LC027 & _LC058 & _LC061 &
_LC063;
-- Node name is '|CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _LC028 $ _EQ067);
_EQ067 = _LC002 & _LC004 & _LC008 & _LC009 & _LC011 & _LC018 &
_LC022 & _LC023 & _LC026 & _LC027 & _LC029 & _LC058 &
_LC061 & _LC063;
-- Node name is '|CNT6:3|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( DOUT15 $ _EQ068);
_EQ068 = DOUT12 & DOUT13 & DOUT14;
-- Node name is '|CNT6:12|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC034', type is buried
_LC034 = LCELL( DOUT23 $ _EQ069);
_EQ069 = DOUT20 & DOUT21 & DOUT22;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda-bill\clock1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,686K
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