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📄 clock1.rpt

📁 vhdl语言编写秒表程序 内含每个模块的源程序
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                                       Logic cells placed in LAB 'D'
        +----------------------------- LC54 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
        | +--------------------------- LC59 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
        | | +------------------------- LC55 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
        | | | +----------------------- LC58 |CLKGEN:1|CNTER2
        | | | | +--------------------- LC61 |CLKGEN:1|CNTER1
        | | | | | +------------------- LC63 |CLKGEN:1|CNTER0
        | | | | | | +----------------- LC50 |CNT6:3|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
        | | | | | | | +--------------- LC62 DOUT8
        | | | | | | | | +------------- LC57 DOUT9
        | | | | | | | | | +----------- LC64 DOUT10
        | | | | | | | | | | +--------- LC53 DOUT11
        | | | | | | | | | | | +------- LC49 DOUT12
        | | | | | | | | | | | | +----- LC51 DOUT13
        | | | | | | | | | | | | | +--- LC52 DOUT14
        | | | | | | | | | | | | | | +- LC56 DOUT15
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC58 -> * * * * - - - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER2
LC61 -> * * * * * - - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER1
LC63 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER0
LC50 -> - - - - - - - - - - - - - - * | - - - * | <-- |CNT6:3|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
LC62 -> - - - - - - - * * * * * * * * | - - - * | <-- DOUT8
LC57 -> - - - - - - - - * * * * * * * | - - - * | <-- DOUT9
LC64 -> - - - - - - - - * * * * * * * | - - - * | <-- DOUT10
LC53 -> - - - - - - - - * - * * * * * | - - - * | <-- DOUT11
LC49 -> - - - - - - * - - - - * * * * | - - * * | <-- DOUT12
LC51 -> - - - - - - * - - - - - * * * | - - * * | <-- DOUT13
LC52 -> - - - - - - * - - - - - * * * | - - * * | <-- DOUT14
LC56 -> - - - - - - * - - - - - * * * | - - * * | <-- DOUT15

Pin
43   -> - - - - - - - - - - - - - - - | - - - - | <-- CLK
11   -> - - - - - - - * * * * * * * * | - * * * | <-- CLR
7    -> - - - - - - - * * * * * * * * | - * * * | <-- ENA
LC4  -> - - * - - - - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER5
LC2  -> - * * - - - - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER4
LC8  -> * * * - - - - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER3
LC17 -> - - - - - - - * * * * - - - - | - * - * | <-- DOUT4
LC21 -> - - - - - - - * * * * - - - - | - * - * | <-- DOUT5
LC20 -> - - - - - - - * * * * - - - - | - * - * | <-- DOUT6
LC19 -> - - - - - - - * * * * - - - - | - * - * | <-- DOUT7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda-bill\clock1.rpt
clock1

** EQUATIONS **

CLK      : INPUT;
CLR      : INPUT;
ENA      : INPUT;

-- Node name is 'DOUT0' = '|CNT10:2|CQI0' 
-- Equation name is 'DOUT0', type is output 
 DOUT0   = TFFE( ENA,  _EQ001, !CLR,  VCC,  VCC);
  _EQ001 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 
              _LC058 &  _LC061 &  _LC063;

-- Node name is 'DOUT1' = '|CNT10:2|CQI1' 
-- Equation name is 'DOUT1', type is output 
 DOUT1   = TFFE( _EQ002,  _EQ003, !CLR,  VCC,  VCC);
  _EQ002 =  DOUT0 & !DOUT1 &  DOUT2 &  ENA
         #  DOUT0 & !DOUT1 & !DOUT3 &  ENA
         #  DOUT0 &  DOUT1 &  ENA;
  _EQ003 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 
              _LC058 &  _LC061 &  _LC063;

-- Node name is 'DOUT2' = '|CNT10:2|CQI2' 
-- Equation name is 'DOUT2', type is output 
 DOUT2   = TFFE( _EQ004,  _EQ005, !CLR,  VCC,  VCC);
  _EQ004 =  DOUT0 &  DOUT1 &  ENA;
  _EQ005 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 
              _LC058 &  _LC061 &  _LC063;

-- Node name is 'DOUT3' = '|CNT10:2|CQI3' 
-- Equation name is 'DOUT3', type is output 
 DOUT3   = TFFE( _EQ006,  _EQ007, !CLR,  VCC,  VCC);
  _EQ006 =  DOUT0 & !DOUT1 & !DOUT2 &  DOUT3 &  ENA
         #  DOUT0 &  DOUT1 &  DOUT2 &  ENA;
  _EQ007 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 
              _LC058 &  _LC061 &  _LC063;

-- Node name is 'DOUT4' = '|CNT10:9|CQI0' 
-- Equation name is 'DOUT4', type is output 
 DOUT4   = TFFE( ENA,  _EQ008, !CLR,  VCC,  VCC);
  _EQ008 = !DOUT0 & !DOUT1 & !DOUT2 & !DOUT3;

-- Node name is 'DOUT5' = '|CNT10:9|CQI1' 
-- Equation name is 'DOUT5', type is output 
 DOUT5   = TFFE( _EQ009,  _EQ010, !CLR,  VCC,  VCC);
  _EQ009 =  DOUT4 & !DOUT5 &  DOUT6 &  ENA
         #  DOUT4 & !DOUT5 & !DOUT7 &  ENA
         #  DOUT4 &  DOUT5 &  ENA;
  _EQ010 = !DOUT0 & !DOUT1 & !DOUT2 & !DOUT3;

-- Node name is 'DOUT6' = '|CNT10:9|CQI2' 
-- Equation name is 'DOUT6', type is output 
 DOUT6   = TFFE( _EQ011,  _EQ012, !CLR,  VCC,  VCC);
  _EQ011 =  DOUT4 &  DOUT5 &  ENA;
  _EQ012 = !DOUT0 & !DOUT1 & !DOUT2 & !DOUT3;

-- Node name is 'DOUT7' = '|CNT10:9|CQI3' 
-- Equation name is 'DOUT7', type is output 
 DOUT7   = TFFE( _EQ013,  _EQ014, !CLR,  VCC,  VCC);
  _EQ013 =  DOUT4 & !DOUT5 & !DOUT6 &  DOUT7 &  ENA
         #  DOUT4 &  DOUT5 &  DOUT6 &  ENA;
  _EQ014 = !DOUT0 & !DOUT1 & !DOUT2 & !DOUT3;

-- Node name is 'DOUT8' = '|CNT10:10|CQI0' 
-- Equation name is 'DOUT8', type is output 
 DOUT8   = TFFE( ENA,  _EQ015, !CLR,  VCC,  VCC);
  _EQ015 = !DOUT4 & !DOUT5 & !DOUT6 & !DOUT7;

-- Node name is 'DOUT9' = '|CNT10:10|CQI1' 
-- Equation name is 'DOUT9', type is output 
 DOUT9   = TFFE( _EQ016,  _EQ017, !CLR,  VCC,  VCC);
  _EQ016 =  DOUT8 & !DOUT9 &  DOUT10 &  ENA
         #  DOUT8 & !DOUT9 & !DOUT11 &  ENA
         #  DOUT8 &  DOUT9 &  ENA;
  _EQ017 = !DOUT4 & !DOUT5 & !DOUT6 & !DOUT7;

-- Node name is 'DOUT10' = '|CNT10:10|CQI2' 
-- Equation name is 'DOUT10', type is output 
 DOUT10  = TFFE( _EQ018,  _EQ019, !CLR,  VCC,  VCC);
  _EQ018 =  DOUT8 &  DOUT9 &  ENA;
  _EQ019 = !DOUT4 & !DOUT5 & !DOUT6 & !DOUT7;

-- Node name is 'DOUT11' = '|CNT10:10|CQI3' 
-- Equation name is 'DOUT11', type is output 
 DOUT11  = TFFE( _EQ020,  _EQ021, !CLR,  VCC,  VCC);
  _EQ020 =  DOUT8 & !DOUT9 & !DOUT10 &  DOUT11 &  ENA
         #  DOUT8 &  DOUT9 &  DOUT10 &  ENA;
  _EQ021 = !DOUT4 & !DOUT5 & !DOUT6 & !DOUT7;

-- Node name is 'DOUT12' = '|CNT6:3|CQI0' 
-- Equation name is 'DOUT12', type is output 
 DOUT12  = TFFE( ENA,  _EQ022, !CLR,  VCC,  VCC);
  _EQ022 = !DOUT8 & !DOUT9 & !DOUT10 & !DOUT11;

-- Node name is 'DOUT13' = '|CNT6:3|CQI1' 
-- Equation name is 'DOUT13', type is output 
 DOUT13  = TFFE( _EQ023,  _EQ024, !CLR,  VCC,  VCC);
  _EQ023 =  DOUT12 & !DOUT13 &  DOUT15 &  ENA
         #  DOUT12 & !DOUT13 & !DOUT14 &  ENA
         #  DOUT12 &  DOUT13 &  ENA;
  _EQ024 = !DOUT8 & !DOUT9 & !DOUT10 & !DOUT11;

-- Node name is 'DOUT14' = '|CNT6:3|CQI2' 
-- Equation name is 'DOUT14', type is output 
 DOUT14  = TFFE( _EQ025,  _EQ026, !CLR,  VCC,  VCC);
  _EQ025 =  DOUT12 & !DOUT13 &  DOUT14 & !DOUT15 &  ENA
         #  DOUT12 &  DOUT13 &  ENA;
  _EQ026 = !DOUT8 & !DOUT9 & !DOUT10 & !DOUT11;

-- Node name is 'DOUT15' = '|CNT6:3|CQI3' 
-- Equation name is 'DOUT15', type is output 
 DOUT15  = DFFE( _EQ027 $  VCC,  _EQ028, !CLR,  VCC,  VCC);
  _EQ027 =  DOUT12 & !DOUT13 &  DOUT14 & !DOUT15
         #  ENA & !_LC050
         # !DOUT15 & !ENA;
  _EQ028 = !DOUT8 & !DOUT9 & !DOUT10 & !DOUT11;

-- Node name is 'DOUT16' = '|CNT10:11|CQI0' 
-- Equation name is 'DOUT16', type is output 
 DOUT16  = TFFE( ENA,  _EQ029, !CLR,  VCC,  VCC);
  _EQ029 = !DOUT12 & !DOUT13 & !DOUT14 & !DOUT15;

-- Node name is 'DOUT17' = '|CNT10:11|CQI1' 
-- Equation name is 'DOUT17', type is output 
 DOUT17  = TFFE( _EQ030,  _EQ031, !CLR,  VCC,  VCC);
  _EQ030 =  DOUT16 & !DOUT17 &  DOUT18 &  ENA
         #  DOUT16 & !DOUT17 & !DOUT19 &  ENA
         #  DOUT16 &  DOUT17 &  ENA;
  _EQ031 = !DOUT12 & !DOUT13 & !DOUT14 & !DOUT15;

-- Node name is 'DOUT18' = '|CNT10:11|CQI2' 
-- Equation name is 'DOUT18', type is output 
 DOUT18  = TFFE( _EQ032,  _EQ033, !CLR,  VCC,  VCC);
  _EQ032 =  DOUT16 &  DOUT17 &  ENA;
  _EQ033 = !DOUT12 & !DOUT13 & !DOUT14 & !DOUT15;

-- Node name is 'DOUT19' = '|CNT10:11|CQI3' 
-- Equation name is 'DOUT19', type is output 
 DOUT19  = TFFE( _EQ034,  _EQ035, !CLR,  VCC,  VCC);
  _EQ034 =  DOUT16 & !DOUT17 & !DOUT18 &  DOUT19 &  ENA
         #  DOUT16 &  DOUT17 &  DOUT18 &  ENA;
  _EQ035 = !DOUT12 & !DOUT13 & !DOUT14 & !DOUT15;

-- Node name is 'DOUT20' = '|CNT6:12|CQI0' 
-- Equation name is 'DOUT20', type is output 
 DOUT20  = TFFE( ENA,  _EQ036, !CLR,  VCC,  VCC);
  _EQ036 = !DOUT16 & !DOUT17 & !DOUT18 & !DOUT19;

-- Node name is 'DOUT21' = '|CNT6:12|CQI1' 
-- Equation name is 'DOUT21', type is output 
 DOUT21  = TFFE( _EQ037,  _EQ038, !CLR,  VCC,  VCC);
  _EQ037 =  DOUT20 & !DOUT21 &  DOUT23 &  ENA
         #  DOUT20 & !DOUT21 & !DOUT22 &  ENA
         #  DOUT20 &  DOUT21 &  ENA;
  _EQ038 = !DOUT16 & !DOUT17 & !DOUT18 & !DOUT19;

-- Node name is 'DOUT22' = '|CNT6:12|CQI2' 
-- Equation name is 'DOUT22', type is output 
 DOUT22  = TFFE( _EQ039,  _EQ040, !CLR,  VCC,  VCC);
  _EQ039 =  DOUT20 & !DOUT21 &  DOUT22 & !DOUT23 &  ENA
         #  DOUT20 &  DOUT21 &  ENA;
  _EQ040 = !DOUT16 & !DOUT17 & !DOUT18 & !DOUT19;

-- Node name is 'DOUT23' = '|CNT6:12|CQI3' 
-- Equation name is 'DOUT23', type is output 
 DOUT23  = DFFE( _EQ041 $  VCC,  _EQ042, !CLR,  VCC,  VCC);
  _EQ041 =  DOUT20 & !DOUT21 &  DOUT22 & !DOUT23
         #  ENA & !_LC034
         # !DOUT23 & !ENA;
  _EQ042 = !DOUT16 & !DOUT17 & !DOUT18 & !DOUT19;

-- Node name is '|CLKGEN:1|:17' = '|CLKGEN:1|CNTER0' 
-- Equation name is '_LC063', type is buried 
_LC063   = TFFE( VCC, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|CLKGEN:1|:16' = '|CLKGEN:1|CNTER1' 
-- Equation name is '_LC061', type is buried 
_LC061   = TFFE( _LC063, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|CLKGEN:1|:15' = '|CLKGEN:1|CNTER2' 
-- Equation name is '_LC058', type is buried 
_LC058   = TFFE( _EQ043, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ043 =  _LC061 &  _LC063;

-- Node name is '|CLKGEN:1|:14' = '|CLKGEN:1|CNTER3' 
-- Equation name is '_LC008', type is buried 
_LC008   = DFFE( _EQ044 $  _LC054, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ044 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 
              _LC054 &  _LC058 &  _LC061 &  _LC063;

-- Node name is '|CLKGEN:1|:13' = '|CLKGEN:1|CNTER4' 
-- Equation name is '_LC002', type is buried 
_LC002   = DFFE( _EQ045 $  _LC059, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ045 = !_LC002 &  _LC004 &  _LC008 & !_LC009 & !_LC011 &  _LC018 & 
             !_LC022 & !_LC023 &  _LC026 &  _LC027 &  _LC028 &  _LC029 & 

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