📄 clock1.rpt
字号:
28 40 C FF t 1 0 1 2 8 7 0 DOUT17 (|CNT10:11|:11)
32 48 C FF t 0 0 0 2 6 6 0 DOUT18 (|CNT10:11|:10)
31 46 C FF t 0 0 0 2 8 6 0 DOUT19 (|CNT10:11|:9)
27 37 C FF t 0 0 0 2 4 3 1 DOUT20 (|CNT6:12|:12)
26 36 C FF t 1 0 1 2 8 3 1 DOUT21 (|CNT6:12|:11)
24 33 C FF t 0 0 0 2 8 3 1 DOUT22 (|CNT6:12|:10)
29 41 C FF t 1 0 1 2 9 3 1 DOUT23 (|CNT6:12|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-bill\clock1.rpt
clock1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 54 D SOFT t 0 0 0 0 4 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
- 59 D SOFT t 0 0 0 0 5 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
- 55 D SOFT t 0 0 0 0 6 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
- 12 A SOFT t 0 0 0 0 7 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
- 43 C SOFT t 0 0 0 0 8 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
- 38 C SOFT t 0 0 0 0 9 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
- 39 C SOFT t 0 0 0 0 10 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
- 42 C SOFT t 0 0 0 0 11 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
- 44 C SOFT t 0 0 0 0 12 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
- 45 C SOFT t 0 0 0 0 13 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
(11) 3 A SOFT t 0 0 0 0 14 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
- 31 B SOFT t 0 0 0 0 15 0 1 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
- 28 B DFFE + t 0 0 0 0 16 4 13 |CLKGEN:1|CNTER14 (|CLKGEN:1|:3)
- 29 B DFFE + t 0 0 0 0 16 4 14 |CLKGEN:1|CNTER13 (|CLKGEN:1|:4)
- 18 B DFFE + t 0 0 0 0 16 4 15 |CLKGEN:1|CNTER12 (|CLKGEN:1|:5)
- 22 B DFFE + t 0 0 0 0 16 4 16 |CLKGEN:1|CNTER11 (|CLKGEN:1|:6)
- 27 B DFFE + t 0 0 0 0 16 4 17 |CLKGEN:1|CNTER10 (|CLKGEN:1|:7)
- 23 B DFFE + t 0 0 0 0 16 4 18 |CLKGEN:1|CNTER9 (|CLKGEN:1|:8)
- 26 B DFFE + t 0 0 0 0 16 4 19 |CLKGEN:1|CNTER8 (|CLKGEN:1|:9)
- 9 A DFFE + t 0 0 0 0 16 4 20 |CLKGEN:1|CNTER7 (|CLKGEN:1|:10)
(6) 11 A DFFE + t 0 0 0 0 16 4 21 |CLKGEN:1|CNTER6 (|CLKGEN:1|:11)
(9) 4 A DFFE + t 0 0 0 0 16 4 22 |CLKGEN:1|CNTER5 (|CLKGEN:1|:12)
- 2 A DFFE + t 0 0 0 0 16 4 23 |CLKGEN:1|CNTER4 (|CLKGEN:1|:13)
(7) 8 A DFFE + t 0 0 0 0 16 4 24 |CLKGEN:1|CNTER3 (|CLKGEN:1|:14)
- 58 D TFFE + t 0 0 0 0 2 4 24 |CLKGEN:1|CNTER2 (|CLKGEN:1|:15)
- 61 D TFFE + t 0 0 0 0 1 4 25 |CLKGEN:1|CNTER1 (|CLKGEN:1|:16)
- 63 D TFFE + t 0 0 0 0 0 4 26 |CLKGEN:1|CNTER0 (|CLKGEN:1|:17)
- 50 D SOFT t 0 0 0 0 4 1 0 |CNT6:3|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
- 34 C SOFT t 0 0 0 0 4 1 0 |CNT6:12|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-bill\clock1.rpt
clock1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC12 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
| +----------- LC3 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
| | +--------- LC9 |CLKGEN:1|CNTER7
| | | +------- LC11 |CLKGEN:1|CNTER6
| | | | +----- LC4 |CLKGEN:1|CNTER5
| | | | | +--- LC2 |CLKGEN:1|CNTER4
| | | | | | +- LC8 |CLKGEN:1|CNTER3
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC12 -> - - - * - - - | * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node6
LC9 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER7
LC11 -> * * * * * * * | * * * - | <-- |CLKGEN:1|CNTER6
LC4 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER5
LC2 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER4
LC8 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER3
Pin
43 -> - - - - - - - | - - - - | <-- CLK
LC54 -> - - - - - - * | * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
LC59 -> - - - - - * - | * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node4
LC55 -> - - - - * - - | * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node5
LC43 -> - - * - - - - | * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
LC28 -> - - * * * * * | * * - - | <-- |CLKGEN:1|CNTER14
LC29 -> - * * * * * * | * * - - | <-- |CLKGEN:1|CNTER13
LC18 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER12
LC22 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER11
LC27 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER10
LC23 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER9
LC26 -> - * * * * * * | * * * - | <-- |CLKGEN:1|CNTER8
LC58 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER2
LC61 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER1
LC63 -> * * * * * * * | * * * * | <-- |CLKGEN:1|CNTER0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-bill\clock1.rpt
clock1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
| +----------------------------- LC28 |CLKGEN:1|CNTER14
| | +--------------------------- LC29 |CLKGEN:1|CNTER13
| | | +------------------------- LC18 |CLKGEN:1|CNTER12
| | | | +----------------------- LC22 |CLKGEN:1|CNTER11
| | | | | +--------------------- LC27 |CLKGEN:1|CNTER10
| | | | | | +------------------- LC23 |CLKGEN:1|CNTER9
| | | | | | | +----------------- LC26 |CLKGEN:1|CNTER8
| | | | | | | | +--------------- LC32 DOUT0
| | | | | | | | | +------------- LC30 DOUT1
| | | | | | | | | | +----------- LC25 DOUT2
| | | | | | | | | | | +--------- LC24 DOUT3
| | | | | | | | | | | | +------- LC17 DOUT4
| | | | | | | | | | | | | +----- LC21 DOUT5
| | | | | | | | | | | | | | +--- LC20 DOUT6
| | | | | | | | | | | | | | | +- LC19 DOUT7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC31 -> - * - - - - - - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node6
LC28 -> * * * * * * * * * * * * - - - - | * * - - | <-- |CLKGEN:1|CNTER14
LC29 -> * * * * * * * * * * * * - - - - | * * - - | <-- |CLKGEN:1|CNTER13
LC18 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER12
LC22 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER11
LC27 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER10
LC23 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER9
LC26 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER8
LC32 -> - - - - - - - - * * * * * * * * | - * - - | <-- DOUT0
LC30 -> - - - - - - - - - * * * * * * * | - * - - | <-- DOUT1
LC25 -> - - - - - - - - - * * * * * * * | - * - - | <-- DOUT2
LC24 -> - - - - - - - - - * - * * * * * | - * - - | <-- DOUT3
LC17 -> - - - - - - - - - - - - * * * * | - * - * | <-- DOUT4
LC21 -> - - - - - - - - - - - - - * * * | - * - * | <-- DOUT5
LC20 -> - - - - - - - - - - - - - * * * | - * - * | <-- DOUT6
LC19 -> - - - - - - - - - - - - - * - * | - * - * | <-- DOUT7
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK
11 -> - - - - - - - - * * * * * * * * | - * * * | <-- CLR
7 -> - - - - - - - - * * * * * * * * | - * * * | <-- ENA
LC38 -> - - - - - - - * - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
LC39 -> - - - - - - * - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
LC42 -> - - - - - * - - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
LC44 -> - - - - * - - - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
LC45 -> - - - * - - - - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
LC3 -> - - * - - - - - - - - - - - - - | - * - - | <-- |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node5
LC9 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER7
LC11 -> * * * * * * * * * * * * - - - - | * * * - | <-- |CLKGEN:1|CNTER6
LC4 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER5
LC2 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER4
LC8 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER3
LC58 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER2
LC61 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER1
LC63 -> * * * * * * * * * * * * - - - - | * * * * | <-- |CLKGEN:1|CNTER0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-bill\clock1.rpt
clock1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC43 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node7
| +--------------------------- LC38 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node0
| | +------------------------- LC39 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node1
| | | +----------------------- LC42 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node2
| | | | +--------------------- LC44 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node3
| | | | | +------------------- LC45 |CLKGEN:1|LPM_ADD_SUB:188|addcore:adder|addcore:adder1|result_node4
| | | | | | +----------------- LC34 |CNT6:12|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
| | | | | | | +--------------- LC35 DOUT16
| | | | | | | | +------------- LC40 DOUT17
| | | | | | | | | +----------- LC48 DOUT18
| | | | | | | | | | +--------- LC46 DOUT19
| | | | | | | | | | | +------- LC37 DOUT20
| | | | | | | | | | | | +----- LC36 DOUT21
| | | | | | | | | | | | | +--- LC33 DOUT22
| | | | | | | | | | | | | | +- LC41 DOUT23
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC34 -> - - - - - - - - - - - - - - * | - - * - | <-- |CNT6:12|LPM_ADD_SUB:73|addcore:adder|addcore:adder0|result_node3
LC35 -> - - - - - - - * * * * * * * * | - - * - | <-- DOUT16
LC40 -> - - - - - - - - * * * * * * * | - - * - | <-- DOUT17
LC48 -> - - - - - - - - * * * * * * * | - - * - | <-- DOUT18
LC46 -> - - - - - - - - * - * * * * * | - - * - | <-- DOUT19
LC37 -> - - - - - - * - - - - * * * * | - - * - | <-- DOUT20
LC36 -> - - - - - - * - - - - - * * * | - - * - | <-- DOUT21
LC33 -> - - - - - - * - - - - - * * * | - - * - | <-- DOUT22
LC41 -> - - - - - - * - - - - - * * * | - - * - | <-- DOUT23
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- CLK
11 -> - - - - - - - * * * * * * * * | - * * * | <-- CLR
7 -> - - - - - - - * * * * * * * * | - * * * | <-- ENA
LC18 -> - - - - - * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER12
LC22 -> - - - - * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER11
LC27 -> - - - * * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER10
LC23 -> - - * * * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER9
LC26 -> - * * * * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER8
LC9 -> * * * * * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER7
LC11 -> * * * * * * - - - - - - - - - | * * * - | <-- |CLKGEN:1|CNTER6
LC4 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER5
LC2 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER4
LC8 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER3
LC58 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER2
LC61 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER1
LC63 -> * * * * * * - - - - - - - - - | * * * * | <-- |CLKGEN:1|CNTER0
LC49 -> - - - - - - - * * * * - - - - | - - * * | <-- DOUT12
LC51 -> - - - - - - - * * * * - - - - | - - * * | <-- DOUT13
LC52 -> - - - - - - - * * * * - - - - | - - * * | <-- DOUT14
LC56 -> - - - - - - - * * * * - - - - | - - * * | <-- DOUT15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-bill\clock1.rpt
clock1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
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