clock1.rpt

vhdl语言编写秒表程序 内含每个模块的源程序

Project Information                                     d:\eda-bill\clock1.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/25/2008 17:13:06

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

clock1    EPM7064LC44-7    3        24       0      53      0           82 %

User Pins:                 3        24       0  



Project Information                                     d:\eda-bill\clock1.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLK' chosen for auto global Clock


Project Information                                     d:\eda-bill\clock1.rpt

** FILE HIERARCHY **



|clkgen:1|
|clkgen:1|lpm_add_sub:188|
|clkgen:1|lpm_add_sub:188|addcore:adder|
|clkgen:1|lpm_add_sub:188|addcore:adder|addcore:adder1|
|clkgen:1|lpm_add_sub:188|addcore:adder|addcore:adder0|
|clkgen:1|lpm_add_sub:188|altshift:result_ext_latency_ffs|
|clkgen:1|lpm_add_sub:188|altshift:carry_ext_latency_ffs|
|clkgen:1|lpm_add_sub:188|altshift:oflow_ext_latency_ffs|
|cnt10:2|
|cnt10:2|lpm_add_sub:73|
|cnt10:2|lpm_add_sub:73|addcore:adder|
|cnt10:2|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt10:2|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:2|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:2|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:11|
|cnt10:11|lpm_add_sub:73|
|cnt10:11|lpm_add_sub:73|addcore:adder|
|cnt10:11|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt10:11|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:11|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:11|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:10|
|cnt10:10|lpm_add_sub:73|
|cnt10:10|lpm_add_sub:73|addcore:adder|
|cnt10:10|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt10:10|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:10|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:10|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt10:9|
|cnt10:9|lpm_add_sub:73|
|cnt10:9|lpm_add_sub:73|addcore:adder|
|cnt10:9|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt10:9|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt10:9|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt10:9|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt6:3|
|cnt6:3|lpm_add_sub:73|
|cnt6:3|lpm_add_sub:73|addcore:adder|
|cnt6:3|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt6:3|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt6:3|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt6:3|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|cnt6:12|
|cnt6:12|lpm_add_sub:73|
|cnt6:12|lpm_add_sub:73|addcore:adder|
|cnt6:12|lpm_add_sub:73|addcore:adder|addcore:adder0|
|cnt6:12|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|cnt6:12|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|cnt6:12|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                            d:\eda-bill\clock1.rpt
clock1

***** Logic for device 'clock1' compiled without errors.




Device: EPM7064LC44-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

              R  R  R                          
              E  E  E                          
              S  S  S                    D     
              E  E  E                    O  D  
              R  R  R                    U  O  
              V  V  V  V  G  G  G  C  G  T  U  
              E  E  E  C  N  N  N  L  N  1  T  
              D  D  D  C  D  D  D  K  D  0  8  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
     ENA |  7                                39 | DOUT9 
RESERVED |  8                                38 | DOUT15 
RESERVED |  9                                37 | DOUT11 
     GND | 10                                36 | DOUT14 
     CLR | 11                                35 | VCC 
RESERVED | 12         EPM7064LC44-7          34 | DOUT13 
   DOUT0 | 13                                33 | DOUT12 
   DOUT1 | 14                                32 | DOUT18 
     VCC | 15                                31 | DOUT19 
   DOUT2 | 16                                30 | GND 
   DOUT3 | 17                                29 | DOUT23 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              D  D  D  D  G  V  D  D  D  D  D  
              O  O  O  O  N  C  O  O  O  O  O  
              U  U  U  U  D  C  U  U  U  U  U  
              T  T  T  T        T  T  T  T  T  
              5  6  7  4        2  1  2  2  1  
                                2  6  1  0  7  
                                               
                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                            d:\eda-bill\clock1.rpt
clock1

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     7/16( 43%)   2/ 8( 25%)   0/16(  0%)  20/36( 55%) 
B:    LC17 - LC32    16/16(100%)   8/ 8(100%)   2/16( 12%)  32/36( 88%) 
C:    LC33 - LC48    15/16( 93%)   8/ 8(100%)   3/16( 18%)  28/36( 77%) 
D:    LC49 - LC64    15/16( 93%)   8/ 8(100%)   3/16( 18%)  21/36( 58%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            26/32     ( 81%)
Total logic cells used:                         53/64     ( 82%)
Total shareable expanders used:                  0/64     (  0%)
Total Turbo logic cells used:                   53/64     ( 82%)
Total shareable expanders not available (n/a):   8/64     ( 12%)
Average fan-in:                                  11.30
Total fan-in:                                   599

Total input pins required:                       3
Total output pins required:                     24
Total bidirectional pins required:               0
Total logic cells required:                     53
Total flipflops required:                       39
Total product terms required:                  149
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  64   (  0%)



Device-Specific Information:                            d:\eda-bill\clock1.rpt
clock1

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  43      -   -       INPUT  G            0      0   0    0    0    0    0  CLK
  11    (3)  (A)      INPUT               0      0   0    0    0   24    0  CLR
   7    (8)  (A)      INPUT               0      0   0    0    0   24    0  ENA


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                            d:\eda-bill\clock1.rpt
clock1

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  13     32    B         FF      t        0      0   0    2   15    7    0  DOUT0 (|CNT10:2|:12)
  14     30    B         FF      t        1      0   1    2   19    7    0  DOUT1 (|CNT10:2|:11)
  16     25    B         FF      t        0      0   0    2   17    6    0  DOUT2 (|CNT10:2|:10)
  17     24    B         FF      t        0      0   0    2   19    6    0  DOUT3 (|CNT10:2|:9)
  21     17    B         FF      t        0      0   0    2    4    7    0  DOUT4 (|CNT10:9|:12)
  18     21    B         FF      t        1      0   1    2    8    7    0  DOUT5 (|CNT10:9|:11)
  19     20    B         FF      t        0      0   0    2    6    6    0  DOUT6 (|CNT10:9|:10)
  20     19    B         FF      t        0      0   0    2    8    6    0  DOUT7 (|CNT10:9|:9)
  40     62    D         FF      t        0      0   0    2    4    7    0  DOUT8 (|CNT10:10|:12)
  39     57    D         FF      t        1      0   1    2    8    7    0  DOUT9 (|CNT10:10|:11)
  41     64    D         FF      t        0      0   0    2    6    6    0  DOUT10 (|CNT10:10|:10)
  37     53    D         FF      t        0      0   0    2    8    6    0  DOUT11 (|CNT10:10|:9)
  33     49    D         FF      t        0      0   0    2    4    7    1  DOUT12 (|CNT6:3|:12)
  34     51    D         FF      t        1      0   1    2    8    7    1  DOUT13 (|CNT6:3|:11)
  36     52    D         FF      t        0      0   0    2    8    7    1  DOUT14 (|CNT6:3|:10)
  38     56    D         FF      t        1      0   1    2    9    7    1  DOUT15 (|CNT6:3|:9)
  25     35    C         FF      t        0      0   0    2    4    7    0  DOUT16 (|CNT10:11|:12)