clkgen.vhd

来自「vhdl语言编写秒表程序 内含每个模块的源程序」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGEN IS
  PORT (CLK:IN STD_LOGIC;
        NEWCLK:OUT STD_LOGIC );
END CLKGEN;
ARCHITECTURE ART OF CLKGEN IS
SIGNAL CNTER:INTEGER RANGE 0 TO 10#29999#;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNTER=10#29999# THEN CNTER<=0;
ELSE CNTER<=CNTER+1;
END IF;
END IF;
END PROCESS;
PROCESS(CNTER)
BEGIN
IF CNTER=10#29999# THEN NEWCLK<='1';
ELSE NEWCLK<='0';
END IF;
END PROCESS;
END ART;