clock_my.vhd

FPGA 实现基于ISA接口的3路编码器计数

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY CLOCK_MY IS 
	PORT( 	 CLK       : IN  STD_LOGIC;					 	--CPLD系统时钟	
	 	
			 SENSOR_A  : IN  STD_LOGIC;					 	--码盘A信号
			 SENSOR_B  : IN  STD_LOGIC;					 	--码盘B信号
			 
			 SENSOR_A2  : IN  STD_LOGIC;					 	--2#码盘A信号
			 SENSOR_B2  : IN  STD_LOGIC;					 	--2#码盘B信号
			
			 SENSOR_A3  : IN  STD_LOGIC;					 	--3#码盘A信号
			 SENSOR_B3  : IN  STD_LOGIC;					 	--3#码盘B信号
			
			 CLR       : IN  STD_LOGIC;					 	--计数器清零信号
			 READ_OE   : IN  STD_LOGIC;						--单片机读信号，高电平有效
			 READ_ADD  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);  --32位计数器，输出选择位
			 												--当1110--1-8位，1101--9-16位，
															--当1011--17-24位,0111--15-32位
															
			 READ_ADD2  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);  --32位计数器，输出选择位
			 												--当1110--1-8位，1101--9-16位，
															--当1011--17-24位,0111--15-32位
															
			 READ_ADD3  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);  --32位计数器，输出选择位
			 												--当1110--1-8位，1101--9-16位，
															--当1011--17-24位,0111--15-32位
															
		     DATA_OUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 	--数据输出	
		 );
END CLOCK_MY;



ARCHITECTURE CLOCK_MY_1 OF CLOCK_MY IS

 	SIGNAL  COUNTER     :  STD_LOGIC_VECTOR(31 DOWNTO 0);  	  --32位计数器
	SIGNAL  SENSOR_AB   :  STD_LOGIC_VECTOR(3 DOWNTO 0);	  --码盘状态:
															  --第四位上一次SENSOR_A
															  --第三位上一次SENSOR_B
															  --第二位现在SENSOR_A
															  --第一位现在SENSOR_B
	SIGNAL  COUNTER2     :  STD_LOGIC_VECTOR(31 DOWNTO 0);  	  --32位计数器
	SIGNAL  SENSOR_AB2   :  STD_LOGIC_VECTOR(3 DOWNTO 0);	  --码盘状态:
															  --第四位上一次SENSOR_A
															  --第三位上一次SENSOR_B
															  --第二位现在SENSOR_A
															  --第一位现在SENSOR_B
	SIGNAL  COUNTER3     :  STD_LOGIC_VECTOR(31 DOWNTO 0);  	  --32位计数器
	SIGNAL  SENSOR_AB3   :  STD_LOGIC_VECTOR(3 DOWNTO 0);	  --码盘状态:
															  --第四位上一次SENSOR_A
															  --第三位上一次SENSOR_B
															  --第二位现在SENSOR_A
															  --第一位现在SENSOR_B
BEGIN   


	PROCESS (CLK)--CLR,READ_OE,READ_ADD)	
	BEGIN	
		IF   CLR = '0' THEN  
			IF READ_ADD ="1110" THEN
		        	COUNTER   <= (OTHERS=>'0');
			     	SENSOR_AB <= (OTHERS=>'0');	
			ELSIF READ_ADD2 = "1110" THEN
					COUNTER2   <= (OTHERS=>'0');
			     	SENSOR_AB2 <= (OTHERS=>'0');
			ELSIF READ_ADD3 = "1110" THEN
					COUNTER3   <= (OTHERS=>'0');
			     	SENSOR_AB3 <= (OTHERS=>'0');
			ELSE DATA_OUT <= (OTHERS=>'Z'); --地址复用通道0的  PWM   输出   
			END IF;		
		ELSE 
		     IF READ_OE = '0' THEN 
		           IF READ_ADD ="1110" THEN  	
	                  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER(  7 DOWNTO 0 );  
		         ELSIF READ_ADD ="1101" THEN
		              DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 15 DOWNTO 8 );  
		         ELSIF READ_ADD ="1011" THEN
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 23 DOWNTO 16 );
				 ELSIF READ_ADD ="0111" THEN  
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 31 DOWNTO 24 );
					
				 ELSIF READ_ADD2 ="1110" THEN  	
	                  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER2(  7 DOWNTO 0 );  
		         ELSIF READ_ADD2 ="1101" THEN
		              DATA_OUT( 7 DOWNTO 0 ) <= COUNTER2( 15 DOWNTO 8 );  
		         ELSIF READ_ADD2 ="1011" THEN
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER2( 23 DOWNTO 16 );
				 ELSIF READ_ADD2 ="0111" THEN  
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER2( 31 DOWNTO 24 ); 
					
				ELSIF READ_ADD3 ="1110" THEN  	
	                  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER3(  7 DOWNTO 0 );  
		         ELSIF READ_ADD3 ="1101" THEN
		              DATA_OUT( 7 DOWNTO 0 ) <= COUNTER3( 15 DOWNTO 8 );  
		         ELSIF READ_ADD3 ="1011" THEN
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER3( 23 DOWNTO 16 );
				 ELSIF READ_ADD3 ="0111" THEN  
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER3( 31 DOWNTO 24 );
		         END IF;
		     ELSE DATA_OUT <= (OTHERS=>'Z');
		     END IF;
		
             IF CLK'EVENT AND ( CLK = '1' ) AND ( CLK'LAST_VALUE = '0' ) THEN		   
				 SENSOR_AB(1) <= SENSOR_A;               --仿真结果显示语句并行执行
				 SENSOR_AB(0) <= SENSOR_B; 				
				 SENSOR_AB(3 DOWNTO 2) <= SENSOR_AB(1 DOWNTO 0); 				   				         					  
			  	 CASE  SENSOR_AB IS 
	 			    WHEN  "0001"  => COUNTER <= COUNTER - 1;
					WHEN  "0111"  => COUNTER <= COUNTER - 1;
					WHEN  "1110"  => COUNTER <= COUNTER - 1;
					WHEN  "1000"  => COUNTER <= COUNTER - 1;					
					WHEN  "0010"  => COUNTER <= COUNTER + 1;
					WHEN  "1011"  => COUNTER <= COUNTER + 1;
					WHEN  "1101"  => COUNTER <= COUNTER + 1;
					WHEN  "0100"  => COUNTER <= COUNTER + 1;					
					WHEN  OTHERS  => COUNTER <= COUNTER;
              	END CASE;
				
				SENSOR_AB2(1) <= SENSOR_A2;               --仿真结果显示语句并行执行
				 SENSOR_AB2(0) <= SENSOR_B2; 				
				 SENSOR_AB2(3 DOWNTO 2) <= SENSOR_AB2(1 DOWNTO 0); 				   				         					  
			  	 CASE  SENSOR_AB2 IS 
	 			    WHEN  "0001"  => COUNTER2 <= COUNTER2 - 1;
					WHEN  "0111"  => COUNTER2 <= COUNTER2 - 1;
					WHEN  "1110"  => COUNTER2 <= COUNTER2 - 1;
					WHEN  "1000"  => COUNTER2 <= COUNTER2 - 1;					
					WHEN  "0010"  => COUNTER2 <= COUNTER2 + 1;
					WHEN  "1011"  => COUNTER2 <= COUNTER2 + 1;
					WHEN  "1101"  => COUNTER2 <= COUNTER2 + 1;
					WHEN  "0100"  => COUNTER2 <= COUNTER2 + 1;					
					WHEN  OTHERS  => COUNTER2 <= COUNTER2;
              	END CASE;

			   SENSOR_AB3(1) <= SENSOR_A3;               --仿真结果显示语句并行执行
				 SENSOR_AB3(0) <= SENSOR_B3; 				
				 SENSOR_AB3(3 DOWNTO 2) <= SENSOR_AB3(1 DOWNTO 0); 				   				         					  
			  	 CASE  SENSOR_AB3 IS 
	 			    WHEN  "0001"  => COUNTER3 <= COUNTER3 - 1;
					WHEN  "0111"  => COUNTER3 <= COUNTER3 - 1;
					WHEN  "1110"  => COUNTER3 <= COUNTER3 - 1;
					WHEN  "1000"  => COUNTER3 <= COUNTER3 - 1;					
					WHEN  "0010"  => COUNTER3 <= COUNTER3 + 1;
					WHEN  "1011"  => COUNTER3 <= COUNTER3 + 1;
					WHEN  "1101"  => COUNTER3 <= COUNTER3 + 1;
					WHEN  "0100"  => COUNTER3 <= COUNTER3 + 1;					
					WHEN  OTHERS  => COUNTER3 <= COUNTER3;
              	END CASE;			  
	  	     END IF;	    --  CLK'EVENT 
	    END IF;             --  CLR = '1'
	END PROCESS; 		

END ARCHITECTURE CLOCK_MY_1;