5050pwm.tan.summary

FPGA 实现基于ISA接口的3路编码器计数

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.086 ns
From           : addr[2]
To             : CLOCK_MY:inst5|DATA_OUT[4]$latch
From Clock     : --
To Clock       : addr[0]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.029 ns
From           : CLOCK_MY:inst5|comb_1011
To             : D[3]
From Clock     : RD
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 14.869 ns
From           : addrSet[0]
To             : EN
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.818 ns
From           : addr[3]
To             : CLOCK_MY:inst5|DATA_OUT[7]$latch
From Clock     : --
To Clock       : RD
Failed Paths   : 0

Type           : Clock Setup: 'myPLL:inst2|altpll:altpll_component|_clk0'
Slack          : 5.332 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 214.22 MHz ( period = 4.668 ns )
From           : pwm:inst7|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[6]
To             : pwm:inst7|lpm_dff0:inst|lpm_ff:lpm_ff_component|dffs[0]
From Clock     : myPLL:inst2|altpll:altpll_component|_clk0
To Clock       : myPLL:inst2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : 33.989 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 166.36 MHz ( period = 6.011 ns )
From           : CLOCK_MY:inst5|SENSOR_AB[1]
To             : CLOCK_MY:inst5|COUNTER[31]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : 1.031 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : CLOCK_MY:inst5|COUNTER[31]
To             : CLOCK_MY:inst5|COUNTER[31]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'myPLL:inst2|altpll:altpll_component|_clk0'
Slack          : 1.045 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11]
To             : pwm:inst8|lpm_counter0:inst11|lpm_counter:lpm_counter_component|cntr_gth:auto_generated|safe_q[11]
From Clock     : myPLL:inst2|altpll:altpll_component|_clk0
To Clock       : myPLL:inst2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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