5050pwm.qsf

FPGA 实现基于ISA接口的3路编码器计数

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		5050PWM_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY 5050PWM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:58:44  JUNE 12, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VHDL -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name BDF_FILE 5050PWM.bdf
set_location_assignment PIN_114 -to addr[9]
set_location_assignment PIN_113 -to addr[8]
set_location_assignment PIN_108 -to addr[7]
set_location_assignment PIN_107 -to addr[6]
set_location_assignment PIN_106 -to addr[5]
set_location_assignment PIN_105 -to addr[4]
set_location_assignment PIN_104 -to addr[3]
set_location_assignment PIN_101 -to addr[2]
set_location_assignment PIN_100 -to addr[1]
set_location_assignment PIN_99 -to addr[0]
set_location_assignment PIN_46 -to addrSet[5]
set_location_assignment PIN_45 -to addrSet[4]
set_location_assignment PIN_44 -to addrSet[3]
set_location_assignment PIN_43 -to addrSet[2]
set_location_assignment PIN_42 -to addrSet[1]
set_location_assignment PIN_41 -to addrSet[0]
set_location_assignment PIN_115 -to AEN
set_location_assignment PIN_153 -to clock
set_location_assignment PIN_128 -to D[7]
set_location_assignment PIN_127 -to D[6]
set_location_assignment PIN_126 -to D[5]
set_location_assignment PIN_125 -to D[4]
set_location_assignment PIN_124 -to D[3]
set_location_assignment PIN_123 -to D[2]
set_location_assignment PIN_122 -to D[1]
set_location_assignment PIN_121 -to D[0]
set_location_assignment PIN_119 -to EN
set_location_assignment PIN_197 -to LED2en
set_location_assignment PIN_237 -to PWMen
set_location_assignment PIN_239 -to PWMout
set_location_assignment PIN_117 -to WR
set_location_assignment PIN_116 -to RD
set_global_assignment -name BDF_FILE 5050PWM_V22.bdf
set_global_assignment -name BDF_FILE 5050PWM_V23.bdf
set_global_assignment -name BDF_FILE 5050PWM_V24.bdf
set_location_assignment PIN_135 -to PHA0
set_global_assignment -name BDF_FILE 5050PWM_V30.bdf
set_global_assignment -name BDF_FILE 5050PWM_V31.bdf
set_location_assignment PIN_136 -to PHB0
set_global_assignment -name BDF_FILE 5050PWM_V32.bdf
set_location_assignment PIN_133 -to PHA1
set_location_assignment PIN_134 -to PHB1
set_location_assignment PIN_131 -to PHA2
set_location_assignment PIN_132 -to PHB2
set_global_assignment -name BDF_FILE 5050PWM_V38.bdf
set_global_assignment -name BDF_FILE 5050PWM_V41.bdf
set_global_assignment -name BDF_FILE 5050PWM_V42.bdf
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name GENERATE_JAM_FILE ON
set_global_assignment -name GENERATE_JBC_FILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name BDF_FILE 5050PWM_V50.bdf
set_location_assignment PIN_238 -to PWMout0
set_location_assignment PIN_240 -to PWMout1