5050pwm.map.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[4\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[4\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[5\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[5\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[6\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[6\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[7\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[7\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/others/maxplus2/74688.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/others/maxplus2/74688.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74688 " "Info: Found entity 1: 74688" {  } { { "74688.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74688.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74688 74688:inst6 " "Info: Elaborating entity \"74688\" for hierarchy \"74688:inst6\"" {  } { { "5050PWM.bdf" "inst6" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 40 320 432 344 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74688:inst6 " "Info: Elaborated megafunction instantiation \"74688:inst6\"" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 40 320 432 344 "inst6" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/others/maxplus2/74377.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/others/maxplus2/74377.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74377 " "Info: Found entity 1: 74377" {  } { { "74377.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74377 74377:inst4 " "Info: Elaborating entity \"74377\" for hierarchy \"74377:inst4\"" {  } { { "5050PWM.bdf" "inst4" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74377:inst4 " "Info: Elaborated megafunction instantiation \"74377:inst4\"" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 656 200 304 848 "inst4" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "5 " "Info: Ignored 5 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "5 " "Info: Ignored 5 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "CLOCK_MY:inst5\|comb_964 CLOCK_MY:inst5\|comb_1011 " "Info: Duplicate LATCH primitive \"CLOCK_MY:inst5\|comb_964\" merged with LATCH primitive \"CLOCK_MY:inst5\|comb_1011\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[7\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[7\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|comb_1011 " "Warning: Latch CLOCK_MY:inst5\|comb_1011 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA WR " "Warning: Ports D and ENA on the latch are fed by the same signal WR" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 400 -48 120 416 "WR" "" } { 392 120 224 408 "wr" "" } { 808 144 200 824 "wr" "" } { 384 584 632 400 "wr" "" } { 1064 272 360 1080 "WR" "" } { 560 792 840 576 "wr" "" } { 752 792 840 768 "wr" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[6\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[5\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[4\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[3\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[2\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[1\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "CLOCK_MY:inst5\|DATA_OUT\[0\]\$latch " "Warning: Latch CLOCK_MY:inst5\|DATA_OUT\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA addr\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal addr\[3\]" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 120 0 168 136 "addr\[9..4\]" "" } { 448 -48 120 464 "addr\[3..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "493 " "Info: Implemented 493 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "452 " "Info: Implemented 452 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 80 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 80 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 07 15:30:01 2008 " "Info: Processing ended: Mon Jul 07 15:30:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}