5050pwm.map.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(78) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(78): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 78 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(79) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(79): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 79 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(80) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(80): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 80 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(81) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(81): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 81 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(82) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(82): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 82 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(83) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(83): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 83 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(84) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(84): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 84 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD2 CLOCK_MY.vhd(86) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(86): signal \"READ_ADD2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 86 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER2 CLOCK_MY.vhd(87) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(87): signal \"COUNTER2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 87 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD2 CLOCK_MY.vhd(88) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(88): signal \"READ_ADD2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 88 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER2 CLOCK_MY.vhd(89) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(89): signal \"COUNTER2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 89 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD2 CLOCK_MY.vhd(90) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(90): signal \"READ_ADD2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 90 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER2 CLOCK_MY.vhd(91) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(91): signal \"COUNTER2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 91 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD2 CLOCK_MY.vhd(92) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(92): signal \"READ_ADD2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 92 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER2 CLOCK_MY.vhd(93) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(93): signal \"COUNTER2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 93 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD3 CLOCK_MY.vhd(95) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(95): signal \"READ_ADD3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 95 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER3 CLOCK_MY.vhd(96) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(96): signal \"COUNTER3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 96 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD3 CLOCK_MY.vhd(97) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(97): signal \"READ_ADD3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 97 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER3 CLOCK_MY.vhd(98) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(98): signal \"COUNTER3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 98 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD3 CLOCK_MY.vhd(99) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(99): signal \"READ_ADD3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 99 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER3 CLOCK_MY.vhd(100) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(100): signal \"COUNTER3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 100 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD3 CLOCK_MY.vhd(101) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(101): signal \"READ_ADD3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 101 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER3 CLOCK_MY.vhd(102) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(102): signal \"COUNTER3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 102 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DATA_OUT CLOCK_MY.vhd(61) " "Warning (10631): VHDL Process Statement warning at CLOCK_MY.vhd(61): inferring latch(es) for signal or variable \"DATA_OUT\", which holds its previous value in one or more paths through the process" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[0\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[0\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[1\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[1\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[2\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[2\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DATA_OUT\[3\] CLOCK_MY.vhd(61) " "Info (10041): Verilog HDL or VHDL info at CLOCK_MY.vhd(61): inferred latch for \"DATA_OUT\[3\]\"" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 61 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}