5050pwm.map.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 18 " "Warning: Port \"PRN\" of type enadff and instance \"18\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 392 288 352 472 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 18 " "Warning: Port \"CLRN\" of type enadff and instance \"18\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 392 288 352 472 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 19 " "Warning: Port \"PRN\" of type enadff and instance \"19\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 480 288 352 560 "19" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 19 " "Warning: Port \"CLRN\" of type enadff and instance \"19\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 480 288 352 560 "19" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 24 " "Warning: Port \"PRN\" of type enadff and instance \"24\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 568 288 352 648 "24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 24 " "Warning: Port \"CLRN\" of type enadff and instance \"24\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 568 288 352 648 "24" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 25 " "Warning: Port \"PRN\" of type enadff and instance \"25\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 656 288 352 736 "25" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 25 " "Warning: Port \"CLRN\" of type enadff and instance \"25\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 656 288 352 736 "25" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pwm:inst\|74377b:inst6 " "Info: Elaborated megafunction instantiation \"pwm:inst\|74377b:inst6\"" {  } { { "pwm.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 200 304 440 280 "inst6" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/others/maxplus2/enadff.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/others/maxplus2/enadff.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 enadff " "Info: Found entity 1: enadff" {  } { { "enadff.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/enadff.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "enadff pwm:inst\|74377b:inst6\|enadff:15 " "Info: Elaborating entity \"enadff\" for hierarchy \"pwm:inst\|74377b:inst6\|enadff:15\"" {  } { { "74377b.bdf" "15" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 304 288 352 384 "15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "pwm:inst\|74377b:inst6\|enadff:15 pwm:inst\|74377b:inst6 " "Info: Elaborated megafunction instantiation \"pwm:inst\|74377b:inst6\|enadff:15\", which is child of megafunction instantiation \"pwm:inst\|74377b:inst6\"" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 304 288 352 384 "15" "" } } } } { "pwm.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 200 304 440 280 "inst6" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/others/maxplus2/16ndmux.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/others/maxplus2/16ndmux.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 16ndmux " "Info: Found entity 1: 16ndmux" {  } { { "16ndmux.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/16ndmux.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "16ndmux 16ndmux:inst1 " "Info: Elaborating entity \"16ndmux\" for hierarchy \"16ndmux:inst1\"" {  } { { "5050PWM.bdf" "inst1" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 352 320 424 640 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "16ndmux:inst1 " "Info: Elaborated megafunction instantiation \"16ndmux:inst1\"" {  } { { "5050PWM.bdf" "" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 352 320 424 640 "inst1" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "myPLL.vhd 2 1 " "Warning: Using design file myPLL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mypll-SYN " "Info: Found design unit 1: mypll-SYN" {  } { { "myPLL.vhd" "" { Text "D:/FPGA/5050PWM_V54/myPLL.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 myPLL " "Info: Found entity 1: myPLL" {  } { { "myPLL.vhd" "" { Text "D:/FPGA/5050PWM_V54/myPLL.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myPLL myPLL:inst2 " "Info: Elaborating entity \"myPLL\" for hierarchy \"myPLL:inst2\"" {  } { { "5050PWM.bdf" "inst2" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 560 584 680 656 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll myPLL:inst2\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"myPLL:inst2\|altpll:altpll_component\"" {  } { { "myPLL.vhd" "altpll_component" { Text "D:/FPGA/5050PWM_V54/myPLL.vhd" 127 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "myPLL:inst2\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"myPLL:inst2\|altpll:altpll_component\"" {  } { { "myPLL.vhd" "" { Text "D:/FPGA/5050PWM_V54/myPLL.vhd" 127 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CLOCK_MY.vhd 2 1 " "Warning: Using design file CLOCK_MY.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLOCK_MY-CLOCK_MY_1 " "Info: Found design unit 1: CLOCK_MY-CLOCK_MY_1" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CLOCK_MY " "Info: Found entity 1: CLOCK_MY" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK_MY CLOCK_MY:inst5 " "Info: Elaborating entity \"CLOCK_MY\" for hierarchy \"CLOCK_MY:inst5\"" {  } { { "5050PWM.bdf" "inst5" { Schematic "D:/FPGA/5050PWM_V54/5050PWM.bdf" { { 936 360 592 1192 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLR CLOCK_MY.vhd(63) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(63): signal \"CLR\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(64) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(64): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD2 CLOCK_MY.vhd(67) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(67): signal \"READ_ADD2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 67 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD3 CLOCK_MY.vhd(70) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(70): signal \"READ_ADD3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 70 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_OE CLOCK_MY.vhd(76) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(76): signal \"READ_OE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 76 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(77) " "Warning (10492): VHDL Process Statement warning at CLOCK_MY.vhd(77): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "D:/FPGA/5050PWM_V54/CLOCK_MY.vhd" 77 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}