5050pwm.map.qmsg

FPGA 实现基于ISA接口的3路编码器计数

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_dff0 pwm:inst\|lpm_dff0:inst " "Info: Elaborating entity \"lpm_dff0\" for hierarchy \"pwm:inst\|lpm_dff0:inst\"" {  } { { "pwm.bdf" "inst" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 464 584 728 544 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff pwm:inst\|lpm_dff0:inst\|lpm_ff:lpm_ff_component " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"pwm:inst\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\"" {  } { { "lpm_dff0.vhd" "lpm_ff_component" { Text "D:/FPGA/5050PWM_V54/lpm_dff0.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pwm:inst\|lpm_dff0:inst\|lpm_ff:lpm_ff_component " "Info: Elaborated megafunction instantiation \"pwm:inst\|lpm_dff0:inst\|lpm_ff:lpm_ff_component\"" {  } { { "lpm_dff0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_dff0.vhd" 77 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_compare1.vhd 2 1 " "Warning: Using design file lpm_compare1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_compare1-SYN " "Info: Found design unit 1: lpm_compare1-SYN" {  } { { "lpm_compare1.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_compare1.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare1 " "Info: Found entity 1: lpm_compare1" {  } { { "lpm_compare1.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_compare1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_compare1 pwm:inst\|lpm_compare1:inst18 " "Info: Elaborating entity \"lpm_compare1\" for hierarchy \"pwm:inst\|lpm_compare1:inst18\"" {  } { { "pwm.bdf" "inst18" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 304 600 728 400 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf" 264 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_compare pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component " "Info: Elaborating entity \"lpm_compare\" for hierarchy \"pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\"" {  } { { "lpm_compare1.vhd" "lpm_compare_component" { Text "D:/FPGA/5050PWM_V54/lpm_compare1.vhd" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component " "Info: Elaborated megafunction instantiation \"pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\"" {  } { { "lpm_compare1.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_compare1.vhd" 71 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_deg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_deg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_deg " "Info: Found entity 1: cmpr_deg" {  } { { "db/cmpr_deg.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cmpr_deg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_deg pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated " "Info: Elaborating entity \"cmpr_deg\" for hierarchy \"pwm:inst\|lpm_compare1:inst18\|lpm_compare:lpm_compare_component\|cmpr_deg:auto_generated\"" {  } { { "lpm_compare.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf" 278 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.vhd 2 1 " "Warning: Using design file lpm_counter0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_counter0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_counter0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 pwm:inst\|lpm_counter0:inst11 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"pwm:inst\|lpm_counter0:inst11\"" {  } { { "pwm.bdf" "inst11" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 312 304 448 392 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/FPGA/5050PWM_V54/lpm_counter0.vhd" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "" { Text "D:/FPGA/5050PWM_V54/lpm_counter0.vhd" 74 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_gth.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_gth.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_gth " "Info: Found entity 1: cntr_gth" {  } { { "db/cntr_gth.tdf" "" { Text "D:/FPGA/5050PWM_V54/db/cntr_gth.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_gth pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated " "Info: Elaborating entity \"cntr_gth\" for hierarchy \"pwm:inst\|lpm_counter0:inst11\|lpm_counter:lpm_counter_component\|cntr_gth:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74377b " "Info: Found entity 1: 74377b" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74377b pwm:inst\|74377b:inst6 " "Info: Elaborating entity \"74377b\" for hierarchy \"pwm:inst\|74377b:inst6\"" {  } { { "pwm.bdf" "inst6" { Schematic "D:/FPGA/5050PWM_V54/pwm.bdf" { { 200 304 440 280 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 15 " "Warning: Port \"PRN\" of type enadff and instance \"15\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 304 288 352 384 "15" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 15 " "Warning: Port \"CLRN\" of type enadff and instance \"15\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 304 288 352 384 "15" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 10 " "Warning: Port \"PRN\" of type enadff and instance \"10\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 216 288 352 296 "10" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 10 " "Warning: Port \"CLRN\" of type enadff and instance \"10\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 216 288 352 296 "10" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 3 " "Warning: Port \"PRN\" of type enadff and instance \"3\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 128 288 352 208 "3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 3 " "Warning: Port \"CLRN\" of type enadff and instance \"3\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 128 288 352 208 "3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "PRN enadff 2 " "Warning: Port \"PRN\" of type enadff and instance \"2\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 40 288 352 120 "2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN enadff 2 " "Warning: Port \"CLRN\" of type enadff and instance \"2\" is missing source signal" {  } { { "74377b.bdf" "" { Schematic "c:/altera/quartus60/libraries/others/maxplus2/74377b.bdf" { { 40 288 352 120 "2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}